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SEE Failure Analysis of Hi-rel ASIC for Spacecraft Applications

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Abstract

Miniaturized electronic devices are essential to improve the performance, reduce the weight and volume, and improve reliability of electronic packages in a spacecraft. With technology scaling, a prime reliability challenge for CMOS devices used in spacecrafts is the occurrence of soft errors due to the propagation of SETs in the space radiation environment. ASICs undergo stringent quality tests to ensure reliable operation of the spacecraft during its mission life. In general, SEE tolerance qualification tests estimate the heavy ion radiation tolerance of CMOS devices for space application. A new SEE test methodology using available scan structure in digital ASICs is proposed. Here, different patterns are loaded in the scan chain which helps to differentiate between SET and SEU soft errors, and test data analysis identifies the SEU fault location. Two different ASIC designs realized in 180 nm CMOS technology are tested in this methodology and detection of SET prone cell is also illustrated.

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Abbreviations

ASIC:

Application specific integrated circuit

CMOS:

Complementary metal oxide semiconductor

DSP:

Digital signal processor

DUT:

Device under test

GPSC:

General purpose scattering chamber

IUAC:

Inter-University Accelerator Centre

IC:

Integrated circuits

ILP:

Integer linear programming

LET:

Linear energy transfer

MUX:

Multiplexer

OBC:

On-board computer

POR:

Power on reset

PROM:

Programmable read only memory

SEE:

Single event effect

SEL:

Single event latch up

SEP:

Single event phenomenon

SER:

Soft error rate

SET:

Single event transient

SEU:

Single event upset

SRAM:

Static random access memory

TCAD:

Technology computer aided design

TMR:

Triple modular redundancy

VLSI:

Very large-scale integration

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Acknowledgements

Authors express heartfelt thanks to anonymous reviewers for providing constructive feedback to improve the content and readability of the manuscript. Also, authors express sincere gratitude to U.R. Rao Satellite Centre, Bengaluru, India, and Semi-Conductor Laboratory, Mohali, India for providing all the support in conducting this research.

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Authors and Affiliations

  1. U R Rao Satellite Centre, ISRO, Bangalore, India

    K. Padmapriya & B. K. S. V. L. Varaprasad

  2. Semi-Conductor Laboratory, Mohali, India

    Debjyoti Mallik

  3. Dayananda Sagar College of Engineering, Bangalore, India

    B. K. S. V. L. Varaprasad

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  1. K. Padmapriya
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  2. B. K. S. V. L. Varaprasad
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Correspondence to K. Padmapriya.

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Padmapriya, K., Varaprasad, B.K.S.V.L. & Mallik, D. SEE Failure Analysis of Hi-rel ASIC for Spacecraft Applications. CEAS Space J (2023). https://doi.org/10.1007/s12567-023-00532-w

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