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Challenges in introducing high-density interconnect technology in printed circuit boards for space applications

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Despite its introduction over 3 decades ago, designing, manufacturing and testing of high-density interconnect (HDI) printed circuit boards (PCBs) remains a topic of discussion. A plethora of advanced manufacturing processes is used to realize HDI PCBs in general and microvias in particular. The introduction of HDI technology for space applications and the pursuit for qualification by the European Space Agency create the need for a critical review of existing test methods. Two categories of HDI technology are considered: two levels of staggered microvias (basic HDI) and three levels of semi-stacked microvias (complex HDI). Several challenges were encountered during the design, testing and evaluation of the basic HDI technology. The main issues were related to the positioning of the microvias with respect to the core via, interconnection stress testing (IST) coupon design, microvia failures and core via performance. ESA has gained significant heritage with interconnection stress testing. IST parameters for mechanical vias and microvias are defined in the current European Cooperation for Space Standardization (ECSS) standard for PCBs. Especially for microvias, recent experiences with failures have led to a revision of the test method. Alternatives microvia test methods as convection reflow assembly simulation and current-induced thermal cycling (CITC) are explored in this study. A thorough understanding of the impact of design variables, manufacturing processes and test parameters is vital for meaningful microvia testing.

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The work in this paper is performed in the frame of an ESA GSTP project (ESA Contract No.: 4000122931/18/NL/LvH). The authors would like to thank Jason Furlong from PWB Interconnect Solutions and all members of the ESA PCB/SMT working group for their valuable insights and feedback.

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Correspondence to Maarten Cauwe.

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Cauwe, M., Vandevelde, B., Nawghane, C. et al. Challenges in introducing high-density interconnect technology in printed circuit boards for space applications. CEAS Space J 15, 101–112 (2023).

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