Abstract
An interesting area of application in wireless data communication is direct-sequence spread spectrum (DSSS). Spread spectrum communication techniques make the signals more robust against interference and jamming. These are based on a concept that narrowband signal is scrambled before transmission in such a way that the signals occupy a much larger part of the radio frequency spectrum. As the digital and the analogue system components are required on the same substrate in today’s mixed-signal chips, the DSSS transmitter system is proposed to be implemented in field-programmable gate array (FPGA)–based platforms and application-specific integrated circuits (ASICs). With a low-power very large-scale integration (VLSI) architecture, sophisticated processing of wide-bandwidth DSSS systems can be exploited in FPGAs/ASICs. In this article, binary pseudo-noise (PN) sequences are generated using a low-power linear feedback shift register (LFSR) in order to spread transmit signals extensively. The proposed low-power design of LFSR and DSSS transmitter with implementation results is illustrated in this paper. Dynamic power dissipation of the proposed DSSS transmitter is reduced up to 15% and 15.6% when compared to the conventional LFSR and the Gold code–based systems respectively. The proposed hardware is implemented in 180-nm technology and operates at 15.36-MHz frequency.
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Jayasanthi, M., Kalaivani, R. Low-power DSSS transmitter and its VLSI implementation. Ann. Telecommun. 76, 537–543 (2021). https://doi.org/10.1007/s12243-021-00837-z
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DOI: https://doi.org/10.1007/s12243-021-00837-z