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Low-latency and high-throughput software turbo decoders on multi-core architectures

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Abstract

In the last few years, with the advent of a software-defined radio (SDR), the processor cores were stated to be an efficient solution to execute the physical layer components. Indeed, multi-core architectures provide both high-processing performance and flexibility, such that they are used in current base station systems instead of dedicated FPGA or ASIC devices. Currently, an extension of the SDR concept is running. Indeed, cloud platforms become attractive for the virtualization of radio access network functions. Actually, they improve the efficiency of the computational resource usage, and thus the global power efficiency. However, the implementation of a physical layer on a Cloud-RAN platform as discussed by Wubben and Paul (2016); Checko et al. (JAMA 17(1):405–426, 2015); Inc (2015); and Wubben et al. (JAMA 31(6):35–44, 2014) or FlexRAN platform as discussed by Wilson (2018); Foukas et al. (2017); Corp. (2017); Foukas et al. (2016) is a challenging task according to the drastic latency and throughput constraints as discussed by Yu et al. (2017) and Parvez (2018). Processing latencies from 10 μ s up to hundred of μ s are required for future digital communication systems. In this context, most of works about software implementations of ECC applications is based on massive frame parallelism to reach high throughput. Nonetheless, they produce unacceptable decoding latencies. In this paper, a new turbo decoder parallelization approach is proposed for x86 multi-core processors. It provides both: high-throughput and low-latency performances. In comparison with all CPU- and GPU-related works, the following results are observed: shorter processing latency, higher throughput, and lower energy consumption. Regarding to the best state-of-the-art x86 software implementations, 1.5 × to 2 × throughput improvements are reached, whereas a latency reduction of 50 × and an energy reduction of 2 × are observed.

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Notes

  1. The 4th streaming SIMD extensions introduced by INTEL in 2006.

  2. The 2nd advanced vector extensions deployed by INTEL in its processors since 2013.

  3. The clang compiler is the only compiler available on the server platform (P3). As we cannot be the administrator of the workstation, it is not possible for us to update the old fedora distribution. In order to have a fair comparison between the platforms, the clang 4 compiler was also used for P1 and P2 platforms.

  4. For small numbers of iterations, it may be necessary to correct the extrapolated values with the information provided in Table 3.

  5. The theoretical limit is 6 instructions per cycle. In practice, it is necessary for these instructions to use different functional units so it is much lower.

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  1. IMS Laboratory, CNRS 5218, Univ. Bordeaux, Bordeaux INP, Bordeaux, France

    Bertrand Le Gal & Christophe Jego

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  1. Bertrand Le Gal
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Le Gal, B., Jego, C. Low-latency and high-throughput software turbo decoders on multi-core architectures. Ann. Telecommun. 75, 27–42 (2020). https://doi.org/10.1007/s12243-019-00727-5

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