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Hardware realization of the robust time–frequency distributions

Abstract

A hardware realization of the L-estimate forms of robust time–frequency distributions is proposed. This hardware realization can be used for instantaneous frequency estimation for signals corrupted by a mixture of impulse and Gaussian noise. The most complex part in the hardware implementation is the block that performs sorting operation. In addition to the continuous realization, a recursive realization of the Bitonic sort network is proposed as well. The recursive approach also provides a fast sorting operation with a significantly reduced number of components. In order to verify the results, the FPGA implementations of the proposed systems were designed.

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Correspondence to Nikola Žarić.

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Žarić, N., Stanković, S. & Uskoković, Z. Hardware realization of the robust time–frequency distributions. Ann. Telecommun. 69, 309–320 (2014). https://doi.org/10.1007/s12243-013-0366-7

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  • DOI: https://doi.org/10.1007/s12243-013-0366-7

Keywords

  • Robust time–frequency distributions
  • Bitonic sort network
  • FPGA implementation