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20 MHz switched-current sample-and-hold circuit with low charge injection

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Abstract

A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and −51.24 dB to 56.53 dB and −54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.

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References

  1. Hughes J B, Bird N C, Macbeth I C. Switched current: A new technique for analog sampled-data signal processing [C]. In: IEEE International Symposium on Circuits and Systems. OR, Portland, USA, 1989.

  2. Sun Y, Wang Y S, Lai F C. Low power high speed switched current comparator [C]. In: International Conference on Mixed Design of Integrated Circuits and Systems. Ciechocinek, Poland, 2007.

  3. Rajaee O, Jahanian A, Bakhtiar M S. A low voltage, high speed, high resolution class AB switched current sample and hold [C]. In: IEEE International Symposium on Circuits and Systems. Kos, Greece, 2006.

  4. Sugimoto Y. A realization of a below-1-V operational and 30-MS/s sample-and hold IC with 56-dB signal-to-noise ratio by applying the current-based circuit approach [J]. IEEE Transactions on Circuits and Systems I, 2004, 51(1): 110–117.

    Article  Google Scholar 

  5. Ozkilic M C, Minaei S, Turkoz S. A current-mode sampleand-hold circuit with high accuracy [C]. In: ISSPA, 9th International Symposium on Signal Process and Its Applications. Sharjah, UAE, 2007.

  6. Sawigun C, Serdijn W A. Low-voltage, low-power, low switching error, class-AB switched current memory cell [J]. Electronics Letters, 2008, 44(12): 706–708.

    Article  Google Scholar 

  7. Yuan Jie. Modeling, quantitative analysis and design of switched-current pipeline A/D converters [J]. IEEE Transactions on Circuits and Systems I, 2009, 56(4): 727–739.

    Article  MathSciNet  Google Scholar 

  8. Sawigun C, Serdijn W A. Analysis and design of a lowvoltage, low-power, high-precision, class-AB current-mode subthreshold CMOS sample and hold circuit [J]. IEEE Transactions on Circuits and Systems I, 2011, 58(7): 1615–1626.

    Article  MathSciNet  Google Scholar 

  9. Lo Ming-Yam, Ki Wing-Hung, Mow Wai-Ho. A 20 MHz switched-current sample-and-hold circuit for current mode analog iterative decoders [C]. In: 12th International Symposium on Integrated Circuits. Singapore, 2009.

  10. Sugimoto Yasuhiro, Gohda Yuji, Tanaka Shigeto. A 35 MS/s and 2 V/2.5 V current-mode sample-and-hold circuit with an input current linearization technique [C]. In: Asian Solid-State Circuits Conference. Hsinchu, Taiwan, China, 2005.

  11. Sugimoto Y. A 1.5-V current-mode CMOS sample-andhold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s [J]. IEEE Journal of Solid-State Circuits, 2001, 36(4): 696–700.

    Article  Google Scholar 

  12. Sawigun C, Serdijn W A. A 24 nW, 0.65-V, 74-dB SNDR, 83-dB DR, class-AB current-mode sample and hold circuit [C]. In: IEEE International Symposium on Circuits and Systems (ISCAS). Paris, France, 2010.

  13. Sugimoto Y, Haigh D G. A current-mode circuit with a linearized input V/I conversion scheme and the realization of a 2-V/2.5-V operational,100-MS/s, MOS SHA [J]. IEEE Transactions on Circuits and Systems I, 2008, 55(8): 2178–2187.

    Article  MathSciNet  Google Scholar 

  14. Nairn D G. Zero-voltage switching in switched current circuits [C]. In: IEEE International Symposium on Circuits and Systems. London, UK, 1994.

  15. Carvajal R G, Ramirez-Angulo J, Lopez-Martin A J et al. The flipped voltage follower: A useful cell for low-voltage low-power circuit design [J]. IEEE Transactions on Circuits and Systems I, 2005, 52(7): 1276–1291.

    Article  Google Scholar 

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Correspondence to Suying Yao  (姚素英).

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Supported by National Natural Science Foundation of China(No.61036004 and No.61076024).

Gao Cen, born in 1981, male, doctorate student.

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Gao, C., Yao, S. & Gao, J. 20 MHz switched-current sample-and-hold circuit with low charge injection. Trans. Tianjin Univ. 19, 47–52 (2013). https://doi.org/10.1007/s12209-013-1957-0

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