Abstract
In this article, we presented a 12-bit 80 MS/s low power successive approximation register (SAR) analog to digital converter (ADC) design. A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency. A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit. The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of > 10.5 bit equivalent number of bits (ENOB), < ±1 least significant bit (LSB) differential nonlinearity (DNL) & integrated nonlinearity (INL), while only consuming less than 2 mA current from a 1.1 V power supply. The calculated figure of merit (FoM) is 17.4 fJ/conversion-step. This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required, such as portable medical imaging.
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Han, G., Wu, B. & Pu, Y. A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging. J. Shanghai Jiaotong Univ. (Sci.) 27, 250–255 (2022). https://doi.org/10.1007/s12204-021-2377-2
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DOI: https://doi.org/10.1007/s12204-021-2377-2
Key words
- successive approximation register (SAR)
- analog to digital converter (ADC)
- medical imaging
- low power
- calibration
- redundancy