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High-Speed Fault-Tolerant Finite Impulse Response Digital Filter on Field Programmable Gate Array

Abstract

Some fast finite impulse response (FIR) filters use a large number of look-up tables (LUTs) to configure distributed random-access memories (RAMs) and save registers. The distributed RAMs store 2M precomputed sums of M permuted operands in order to simplify the accumulation, which lays similarity to the solution of Boolean satisfiability (SAT) problem. In this work, a high-speed fault-tolerant FIR digital filter on field programmable gate array (FPGA) is proposed for hardware implementation. A shift register and an RAM are used to arrange the data flow. Generally, an N-tap digital filter only requires N embedded multipliers on FPGA. The better performance is due to high-radix words and low-latency operations. A 32-tap 8-bit FIR digital filter enjoys a throughput of 9.17 MB/s, taking 109 ns to calculate one convolution. In addition, a fault-tolerant scheme by majority logic is used to correct real-time errors within digital filters.

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Correspondence to Tao Wu.

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Wu, T. High-Speed Fault-Tolerant Finite Impulse Response Digital Filter on Field Programmable Gate Array. J. Shanghai Jiaotong Univ. (Sci.) 26, 554–558 (2021). https://doi.org/10.1007/s12204-020-2214-z

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Key words

  • finite impulse response (FIR)
  • digital filter
  • fault-tolerant
  • fast architecture

CLC number

  • TN 911.72

Document code

  • A