Skip to main content
Log in

Design and implementation of a data-driven dynamical reconfigurable cell array

  • Published:
Journal of Shanghai Jiaotong University (Science) Aims and scope Submit manuscript

Abstract

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. SMITH M C, PETERSON G D. Optimization of shared high-performance reconfigurable computing resources [J]. ACM Transactions on Embedded Computing Systems, 2012, 11(2): 36.

    Article  Google Scholar 

  2. MIYAMORI T, OLUKOTUN K. A Quantitative analysis of reconfigurable coprocessors for multimedia applications [C]//IEEE Symposium on FPGAs for Custom Computing Machines. [s.l.]: IEEE, 1998: 2–11.

    Google Scholar 

  3. SINGH H, LEE M H, LU G M, et al. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications [J]. IEEE Transactions on Computers, 2000, 49(5): 465–481.

    Article  Google Scholar 

  4. VEREDAS F J, SCHEPPLER M, MOFFAT W, et al. Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes [C]//International Conference on Field Programmable Logic and Applications. [s.l.]: IEEE, 2005: 106–111.

    Google Scholar 

  5. PACT XPP Technologies. XPP-III processor overview [EB/OL]. (2006-07-13). http://www.pactxpp.com.

  6. ZHU M, LIU L B, YIN S Y, et al. A reconfigurable multi-processor SoC for media applications [C]//IEEE International Symposium on Circuits and Systems. [s.l.]: IEEE, 2010: 2011–2014.

    Google Scholar 

  7. LI T, XIAO L Z, HUANG H C, et al. PAAG: A polymorphic array architecture for graphics and image processing [C]//International Symposium on Parallel Architectures, Algorithms and Programming. [s.l.]: IEEE, 2012: 242–249.

    Google Scholar 

  8. COMPTON K, HAUCK S. Reconfigurable computing: A survey of systems and software [J]. ACM Computing Surveys, 2002, 34(2): 171–210.

    Article  Google Scholar 

  9. AMANO H. A survey on dynamically reconfigurable processors [J]. IEICE Transactions on Communications, 2006, 89 (12): 3179–3187.

    Article  Google Scholar 

  10. NAJJAR W A, LEE E A, GAO G R. Advances in the dataflow computational model [J]. Parallel Computing, 2000, 25(13/14): 1907–1929.

    Google Scholar 

  11. ROSENFELD J, FRIEDMAN E G. Design methodology for global resonant H-tree clock distribution networks [J]. IEEE Transactions on Very Large Scale Integration Systems, 2007, 15(2): 135–148.

    Article  Google Scholar 

  12. Khronos Vision Working Group. The OpenVX specification [EB/OL]. (2014-10-07). https://www. khronos.org/registry/vx/specs/1.0.1/html/index.html.

  13. HOGENAUER E B. An economical class of digital filters for decimation and interpolation [J]. IEEE Transactions on Acoustics Speech and Signal Processing, 1981, 29(2): 155–162.

    Article  Google Scholar 

  14. MONSON J, WIRTHLIN M, HUTCHINGS B L. Optimization techniques for a high level synthesis implementation of the Sobel filter [C]//2013 International Conference on IEEE Reconfigurable Computing and FPGAs (ReConFig). [s.l.]: IEEE, 2013: 1–6.

    Google Scholar 

  15. SHAN R, LI T, HAN J G. The buffered edge reconfigurable cell array and its applications [C]//2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications. [s.l.]: IEEE, 2013: 1023–1030.

    Chapter  Google Scholar 

  16. DORE A, LASRADO S. Performance analysis of Sobel edge filter on heterogeneous system using OPENCL [J]. International Journal of Research in Engineering and Technology, 2014, 3(15): 53–57.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rui Shan  (山 蕊).

Additional information

Foundation item: the National Natural Science Foundation of China (Nos. 61136002, 61272120, 61634004 and 61602377), the Shaanxi Provincial Co-ordination Innovation Project of Science and Technology (No. 2016KTZDGY02-04-02), the Shaanxi Provincial Science and Technology Research Fund (Nos. 2013KTZB01-07, 2014ZS-08 and S2015TQGY0166), and the Fund of Shaanxi Education Bureau (No. 2050205)

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Shan, R., Li, T., Jiang, L. et al. Design and implementation of a data-driven dynamical reconfigurable cell array. J. Shanghai Jiaotong Univ. (Sci.) 22, 493–503 (2017). https://doi.org/10.1007/s12204-017-1862-0

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12204-017-1862-0

Key words

CLC number

Navigation