Abstract
Using embedded thermal sensors, dynamic thermal management (DTM) techniques measure runtime thermal behavior of high-performance microprocessors so as to prevent thermal runaway situations. The number of placed sensors should be minimized, while guaranteeing accurate tracking of hot spots and full thermal characterization. In this paper, we propose a rigid sensor allocation and placement technique for determining the minimal number of thermal sensors and the optimal locations while satisfying an expected accuracy of hot spot temperature error based on dual clustering. We analyze the false alarm rates of hot spots using the proposed methods in noise-free, with noise and sensor calibration scenarios, respectively. Experimental results confirm that our proposed methods are capable of accurately characterizing the temperatures of microprocessors.
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LIN S C, BANERJEE K. Cool chips: Opportunities and implications for power and thermal management [J]. IEEE Transactions on Electron Devices, 2008, 55(1): 245–255.
JAYASEELAN R, MITRA T. Dynamic thermal management via architectural adaptation [C]//Proceedings of the 46th Annual Design Automation Conference. San Francisco, California, USA: IEEE, 2009: 484–489.
SHI B, ZHANG Y, SRIVASTAVA A. Dynamic thermal management under soft thermal constraints [J]. IEEE Transactions on Very large Scale Integration Systems, 2013, 21(11): 2045–2054.
LONG J, MEMIK S O, MEMIK G, et al. Thermal monitoring mechanisms for chip multiprocessors [J]. ACM Transactions on Architecture and Code Optimization, 2008, 5(2): 9:1-9:33.
MEMIK S O, MUKHERJEE R, NI M, et al. Optimizing thermal sensor allocation for microprocessors [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 2008, 27(3): 516–527.
ZHANG Y, SRIVASTAVA A. Accurate temperature estimation using noisy thermal sensors [C]// Proceedings of the 46th Annual Design Automation Conference. San Francisco, California, USA: IEEE, 2009: 472–477.
ZHANG Y, SRIVASTAVA A. Accurate temperature estimation using noisy thermal sensors for Gaussian and non-Gaussian cases [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(9): 1617–1626.
NOWROZ A N, COCHRAN R, REDA S. Thermal monitoring of real processors: Techniques for sensor allocation and full characterization [C]//Proceedings of the 47th Design Automation Conference. Anaheim, California, USA: IEEE, 2010: 56–61.
REDA S, COCHRAN R, NOWROZ A N. Improved thermal tracking for processors using hard and soft Sensor allocation techniques [J]. IEEE Transactions on Computers, 2011, 60(6): 841–851.
RANIERI J, VINCENZI A, CHEBIRA A, et al. Eigen-Maps: Algorithms for optimal thermal maps extraction and sensor placement on multicore processors [C]//Proceedings of the 49th Annual Design Automation Conference. San Francisco, California, USA: IEEE, 2012: 636–641.
WANG W. Reach on sobel operator for vehicle recognition [C]//2009 International Joint Conference on Artificial Intelligence. Hainan Island: IEEE, 2009: 448–451.
MUKHERJEE R, MEMIK S O. Systematic temperature sensor allocation and placement for microprocessors [C]//Proceedings of the 43rd annual Design Automation Conference. San Francisco, California, USA: IEEE, 2006: 542–547.
LIN C R, LIU K H, CHEN M S. Dual clustering: Integrating data clustering over optimization and constraint domains [J]. IEEE Transactions on Knowledge and Data Engineering, 2005, 17(5): 628–637.
JIAO L M, LIU Y L, ZOU B. Self-organizing dual clustering considering spatial analysis and hybrid distance measures [J]. Science China Earth Sciences, 2011, 54(8): 1268–1278.
BHATTACHARYA P, GAVRILOVA M L. Voronoi diagram in optimal path planning [C]//4th International Symposium on Voronoi Diagrams in Science and Engineering. Glamorgan, England: IEEE, 2007: 38–47.
KESSLER R E. The alpha 21264 microprocessor [J]. IEEE Micro, 1999, 19(2): 24–36.
HENNING J. SPEC CPU2000: Measuring CPU performance in the new millennium [J]. IEEE Computer, 2000, 33(7): 28–35.
BURGER D C, AUSTIN T M. The simplescalar tool set, version 2. 0 [J]. ACM SIGARCH Computer Architecture News, 1997, 25(3): 13–25.
BROOKS D, TIWARI V, MARTONOSI M. Wattch: A framework for architectural-level power analysis and optimizations [C]//Proceedings of the 27th International Symposium on Computer Architecture. Vancouver, British Columbia, Canada: IEEE, 2000: 83–94.
LIAO W, HE L, LEPAK K M. Temperature and supply voltage aware performance and power modeling at microarchitecture level [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(7): 1042–1053.
WILTON S, JOUPPI N P. Cacti: An enhanced cache access and cycle time model [J]. IEEE Journal Solid-State Circuits, 1996, 31(5): 677–688.
HUANG W, GHOSH S, VELUSAMY S, et al. Hotspot: A compact thermal modeling methodology for early-stage VLSI design [J]. IEEE Transactions on VLSI Systems, 2006, 14(5): 501–513.
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Foundation item: the National Natural Science Foundation of China (No. 61501377)
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Li, X., Zhou, W. & Jiang, W. Rigid sensor allocation and placement technique for reducing the number of sensors in thermal monitoring. J. Shanghai Jiaotong Univ. (Sci.) 22, 481–492 (2017). https://doi.org/10.1007/s12204-017-1861-1
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DOI: https://doi.org/10.1007/s12204-017-1861-1