DC gain analysis of scaled CMOS op amp in Sub-100 nm technology nodes: A research based on channel length modulation effect

Abstract

Metal-oxide-semiconductor field effect transistor (MOSFET) intrinsic gain degradation caused by channel length modulation (CLM) effect is examined. A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4 (BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced, which only needs a few technology parameters. With this transistor intrinsic gain model, complementary metal-oxide-semiconductor (CMOS) operational amplifier (op amp) DC gain could be predicted. A two-stage folded cascode op amp is used as an example in this work. Non-minimum length device is used to improve the op amp DC gain. An improvement of 20 dB is proved when using doubled channel length design. Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain. After these, a full op amp DC gain scaling roadmap is proposed, from 130 nm technology node to 32 nm technology node. Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB. Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology. The prediction based on our simplified gain model agrees with SPICE simulation results.