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High throughput compact area architecture of XXTEA for IoT application

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Abstract

Lightweight cryptography has been one of such fields which is used in resource constrained environments. XXTEA is a popular and efficient lightweight block cipher that can work on minimum 64-bit block size and provides sufficient security as compared to TEA and XTEA block cipher. In this paper, XXTEA lightweight block cipher with 128 bit block size has been used for image encryption by using pipelined hardware architecture which significantly improved the speed with little area overhead. For the hardware architecture of XXTEA, to store the image data, a high level memory interface has been used. The proposed design has been implemented in FPGA and ASIC platforms. The frequency has been improved by 85.9% and has an efficiency of seven time more than the previous literature in FPGA platform. Security analysis has been performed to estimate the security strength of the XXTEA and derived various parameters like histogram, key sensitivity, key space, pixel correlation co-efficient, differential attack, etc.

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Authors and Affiliations

  1. Department of Microelectronics and VLSI, Chhattisgarh Swami Vivekanand Technical University (CSVTU), Durg, Chhattisgarh, 491107, India

    Zeesha Mishra

  2. Department of Electronics and Communication Engineering, National Institute of Technology Raipur, G. E. Road, Raipur, Chhattisgarh, 492010, India

    Bibhudendra Acharya

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  1. Zeesha Mishra
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  2. Bibhudendra Acharya
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Correspondence to Bibhudendra Acharya.

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Mishra, Z., Acharya, B. High throughput compact area architecture of XXTEA for IoT application. Sādhanā 48, 80 (2023). https://doi.org/10.1007/s12046-023-02135-x

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  • DOI: https://doi.org/10.1007/s12046-023-02135-x

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