Skip to main content
SpringerLink
Log in

An optimization of low power 4-bit PAL FIR filter using adiabatic techniques

  • Published:
Sādhanā Aims and scope Submit manuscript

Abstract

This paper proposes a 4-bit FIR filter useful in communication and many application of Digital Signal Processing (DSP) using fully adiabatic technology PAL, which reduces all parametric performance and power consumptions. This research work presents a fully adiabatic low power and high speed efficient FIR Filter design and compared with CMOS FIR filters. The PAL FIR filter is designed using reversible logic and it is simulated and synthesized using CADENCE digital lab for different parameters like transition frequency variations, supply voltage variations and load capacitance variation. This architecture includes the low power dissipation due to adiabatic technology and logarithmic multiplier to reduce the hardware requirements. Synthesis reports show that the proposed PAL FIR filter is capable of reducing approximately 75% power dissipation as compared to CMOS FIR filter at different frequencies, supply voltage and capacitance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14

Similar content being viewed by others

References

  1. Knapp M C, Kindlmann P J and Papaefthymiou M C 1997 Design and evaluation of adiabatic arithmetic units. Analog Integr. Circuits Signal Process. 14: 71–79

    Article  Google Scholar 

  2. Sheetal M S and Vigneswaran T 2014 High speed and efficient 4-Tap FIR filter design using modified ETA and multipliers. Int. J. Eng. Technol. 5: 2159–2160

    Google Scholar 

  3. Le Maire J, Brunie N, De Dinechin F and Muller J-M 2016 Computing floating-point logarithms with fixed-point operations. In: IEEE 23rd Symposium on Computer Arithmetic, Santa Clara, United States

  4. Mohanty B K, Mehar P K, Singhal S K and Swamy M N S 2016 A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integr. VLSI J. 54: 37–46

    Article  Google Scholar 

  5. Rai A, Hazarika K and Jain M 2019 Adaptive volterra filters for active control of nonlinear noise processes. Lecture Notes in Electrical Engineering Springer, 509

  6. Singh A, Hasan Z and Malviya U 2014 NMOS low pass filter as sample and hold circuit. Int. J. Sci. Res. Eng. Technol. 3(9): 1282–1283

    Google Scholar 

  7. Karunakaran S and Kasturi N 2012 VLSI implementation of FIR filter using computational sharing multiplier based on high speed carry select adder. Am. J. Appl. Sci. 9(12): 2028–2045

    Article  Google Scholar 

  8. Burlingame E and Spencer R 2000 An analog CMOS high-speed continuous-time FIR filter. In Proceedings of the 26th European Solid-State Circuits Conference Stockholm Sweden, 288–291

  9. Gupta N 2013 Power aware & high-speed booth multiplier based on adiabatic logic. Int. J. Innov. Eng. Technol. 2(3): 297–303

    Google Scholar 

  10. Taheri M, Akbar R, Safaei F and Moaiyeri M 2016 Comparative analysis of adiabatic full adder cells in CNFET technology. Eng. Sci. Technol. Int. J. 19(4): 2119–2128

    Google Scholar 

  11. William C A and Lars J S 1994 Low power digital system based on adiabatic-switching principal. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 2(4): 398–407

    Article  Google Scholar 

  12. Jesmin J 2015 Adaptive fir filter with optimized area and power using modified inner-product block. Int. J. Innov. Res. Comput. Commun. Eng. 3(9): 7973–7981

    Google Scholar 

  13. Chandorkar A N and Singh G 2006 Design of low power 4-tap 8-bit adiabatic FIR filter. In Proceedings international conference on computer design & conference on computing in nanotechnology, 112–117

  14. Kao J C, Ma W H, Sathe V S and Papaefthymiou M 2012 Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 20(6): 977–988

    Article  Google Scholar 

  15. Duncan M J 2003 Improved Mitchell based logarithmic multiplier for low power DSP applications. In IEEE Int’l System on a Chip Conf, 17–20

  16. Sun Y and Kim MS 2011 A high-performance 8-Tap FIR filter using logarithmic number system. In IEEE International Conference on Communication, 1–5

  17. Nandan Durgesh, Kanungo Jitendra and Mahajan Anurag 2017 An Efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition. Integr. VLSI J. 58: 134–141

    Article  Google Scholar 

  18. Park J 2004 Computation sharing programmable FIR filter for low-power and high-performance applications. JSSC 39: 348–356

    Google Scholar 

  19. Lim J, Kim D G and Chae S-I 1999 A 16-bit carry lookahead adder using reversible energy recovery logic for ultra-low-energy systems. IEEE J. Solid-State Circuits 34(6): 898–903

    Article  Google Scholar 

  20. Alioto M and Palumbo G 2000 Performance evaluation of adiabatic gates. IEEE Trans. Circuits Syst. 47(9): 1297–1308

    Article  Google Scholar 

  21. Staszewski R B, Muhammad K and Balsara P 2000 A 500-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. JSSC 35: 1205–1210

    Google Scholar 

  22. Kim S, Ziesler C H and Papaefthymiou M C 2003 A true single-phase energy recovery multiplier. IEEE Transaction on Very Large Scale Integration Systems 11(2): 194–207

    Article  Google Scholar 

  23. Kumngern M, Nonthaputha T and Khateb F 2018 Low-power sample and hold circuits using current conveyor analogue switches. IET Circuits Devices Syst. 12(4): 397–402

    Article  Google Scholar 

  24. Sewter J C and Chan A 2006 A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. IEEE J. Solid-State Circuits 41(4): 909–917

    Article  Google Scholar 

  25. Dilip K B and Bharathi M 2013 Design of energy efficient arithmetic circuit using charge recovery adiabatic logic. Int. J. Eng. Trends Technol. 4(1): 32–40

    Google Scholar 

  26. Ching L and Ling O 1998 Low-power and low voltage D-flip flop. IEEE Lett. 34: 541–542

    Google Scholar 

  27. Weste N H E and Harris D F 2004 CMOS VLSI design a circuits and systems perspective. Pearson, New York

    Google Scholar 

  28. Priya A and Rai A 2014 Adiabatic technique for power efficient logic circuit design. Int. J. Electron. Commun. Technol. 5(1): 70–78

    Google Scholar 

  29. Proakis J G and Manolakis G D 2007 Digital Signal Processing Principles Algorithms and Applications. PEARSON publication

  30. Rai A, Singh M and Prasad S V A V 2009 VLSI implementation & design of complex multiplier for FFT using ASIC-VLSI. Int. J. Electron. Eng. 1(1): 103–112

    Google Scholar 

  31. Bir P, Karatangi S V and Rai A 2020 Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models. J. Supercomput. 76(9): 7394–7415

    Article  Google Scholar 

Download references

Acknowledgment

The authors are deeply thankful to Puneet Kumar Mishra and Om Prakash for their fundamental administrative and technical support.

Author information

Authors and Affiliations

  1. ECE Department, GL Bajaj Institute of Technology and Management, Greater Noida, Uttar Pradesh, India

    Amrita Rai

Authors
  1. Amrita Rai
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Amrita Rai.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Rai, A. An optimization of low power 4-bit PAL FIR filter using adiabatic techniques. Sādhanā 48, 84 (2023). https://doi.org/10.1007/s12046-023-02132-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s12046-023-02132-0

Keywords

Search

Navigation