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Compact modeling of through silicon vias for thermal analysis in 3-D IC structures

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Abstract

Heat mitigation is a major challenge in 3-D IC (Three-Dimensional Integrated Circuit) realization. A study of analytical thermal behavior of the TSV (Through Silicon Via) is very important. Simple and compact yet other models were found deficient to solve this problem in the literature survey. In this paper, resistance networks are used to model the heat transfer of the TSVs in both vertical and horizontal directions in simpler and compact models. The accuracy of such models is compared to those from the commercially available CFD (computational fluid dynamics) tool. The errors of corrections between the tool and developed models are corrected by multiplication factors, resulting in 4.18% accuracy. Varying the thicknesses of a liner, filler, soldering, and substrate materials is studied concerning heat transfer and physical behavior of three planar TSV stacked systems. The major purpose is to incorporate both vertical and horizontal thermal resistance networks captured more accurately in heat dissipation paths. Proposed models of TSVs can be used in the active interposer simulations or the face-to-face fabrication stacked methods of the 3-D IC structures.

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Abbreviations

R 1, R 4, R 7 :

Resistances of the silicon substrate (Ω)

R s :

Resistance of the heatsink (Ω)

R 3, R 6, R 9 :

Resistances of the liner (Ω)

R 2, R 5, R 8 :

Resistances of the filler (Ω)

R x, R y :

Resistances of the bonding material (Ω)

R a, R c, R d, R f :

Resistances of TSV pads (Ω)

R b, R e :

Resistances of the soldering material (Ω)

ΔT :

Temperature difference (°C)

T 0–T 7 :

Temperature nodes of the 3-D IC stack (no units)

q 1, q 2, q 3 :

Voltage sources (W/mm3)

x 1, x 2 :

Fitting coefficients (no units)

A 0 :

Footprint of experimental area (μm2)

A :

Larger area of the silicon substrate (μm2)

tSi :

Thickness of the silicon substrate (μm2)

t D :

Thickness of the ILD (Inter-Layer Dielectric) layer (μm2)

t b :

Thickness bonding layer (μm2)

k si :

Thermal conductivity of silicon substrate (W/m K)

k D :

Thermal conductivity of ILD (W/m K)

k b :

Thermal conductivity of bonding material (W/m K)

k L :

Thermal conductivity of liner (W/m K)

k f :

Thermal conductivity of filler (W/m K)

k s :

Thermal conductivity of soldering material (W/m K)

r :

Radius of TSV (µm)

t L :

Thickness of insulator liner (µm)

l ext :

TSV segment, extended into silicon substrates (μm2)

V p :

Volume of TSV pad (μm3)

V s :

Volume of soldering bump (μm3)

h :

Height/thickness of the soldering bump (µm)

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Acknowledgements

We thank Mr. Venkat Ghanta, Mr. Saumitra Kale, and Mr. Harshil Shah, the Directors of Engineering at Cisco Inc, for their continuous encouragement. We also thank Head of the Electronics and Communications Engineering Department, Dr. Arathi Shankar, B M S College of Engineering, for facilitating the project, on behalf of the college and Visveswaraya Technological University.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, B M S College of Engineering, Visvesvaraya Technological University, Bangalore, 560019, India

    CHANDRASHEKHAR V PATIL

  2. Department of Medical Electronics Engineering, B M S College of Engineering, Visvesvaraya Technological University, Bangalore, 560019, India

    M S SUMA

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Correspondence to CHANDRASHEKHAR V PATIL.

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PATIL, C.V., SUMA, M.S. Compact modeling of through silicon vias for thermal analysis in 3-D IC structures. Sādhanā 46, 35 (2021). https://doi.org/10.1007/s12046-020-01549-1

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