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Effects of the physical parameter on gate all around FET

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Abstract

As the devices are getting compact, the size of transistors reduces day by day; however, with certain limitations. Due to miniaturization, the characteristics of the transistor change due to quantum mechanical effects and the present scenario, analytically modeled surface potential-based gate all around (GAA) FET model by solving 1-D Poisson’s equation, approximation method and using necessary boundary condition. Here, the change in channel material (Si, InP, GaAs, InAs and Ge), channel radius (varied from 6 nm to 10 nm), oxide thickness (changed from 2 nm to 5 nm), drain to source voltage (varied from −0.5 V to 0.5 V), Source/Drain doping (varied from 1017 to 1022/cm3) and temperature (from 0 to 300 K) of the transistor, surface potential changes from −1.6 V to 1.3 V approx. respectively, considered as the GAA FET parameters. The proposed novel model exhibits better control over hot carrier effect, Drain Induced Barrier Lowering (DIBL), reduced threshold voltage and other such short channel effects in the GAA FET. Moreover, the I–V characteristics of the GAA FET were analyzed. The MATLAB code is used for modeling of the GAA FET nanowire transistor.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim Manipal University, Majhitar, Rangpo, 737136, India

    Amit Agarwal & P C Pradhan

  2. Department of Physics, National Institute of Technology, Imphal, 795004, India

    Bibhu P Swain

Authors
  1. Amit Agarwal
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  2. P C Pradhan
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  3. Bibhu P Swain
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Correspondence to Bibhu P Swain.

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Agarwal, A., Pradhan, P.C. & Swain, B.P. Effects of the physical parameter on gate all around FET. Sādhanā 44, 248 (2019). https://doi.org/10.1007/s12046-019-1232-8

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  • DOI: https://doi.org/10.1007/s12046-019-1232-8

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