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Sadhana

, Volume 38, Issue 4, pp 645–651 | Cite as

A new universal gate for low power SoC applications

  • M GEETHA PRIYA
  • K BASKARAN
Article

Abstract

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.

Keywords

Low power CMOS pass-transistor NAND gate Koomey’s law 

References

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Copyright information

© Indian Academy of Sciences 2013

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAmrita Vishwa VidyapeethamCoimbatoreIndia
  2. 2.Department of Computer Science and EngineeringGovernment College of TechnologyCoimbatoreIndia

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