Abstract
Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper, a parallel finite-impulse response (FIR) filter structure based on polyphase filtering is used to achieve high-speed matched filter in quadrature phase-shift keying (QPSK) demodulation up to 800 Mb · s−1. First, a window function is employed of to obtain impulse response of matched filter. Second, the high-speed parallel FIR structure is presented based on polyphase filtering. Then, the filter with EP2S180F1020 on the Quartus II 7.2 platform is achieved. The final results show that the design is correct and can implement high-speed matched filtering, wherein the equivalent frequency of which is up to 2 037 MHz. In addition, this scheme is easy to realize, which brings great value to the application of this filter in high-speed matched filters design in demodulation systems.
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Foundation item: Supported by the National High Technology Research and Development Program of China (863 Program) (2006AA040307)
Biography: ZHANG Qinglin, male, Ph. D. candidate, research direction: high-speed data acquisition and processing and software defined radio.
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Zhang, Q., Chen, S., Luo, Y. et al. High-speed parallel matched filter designing and FPGA implementation. Wuhan Univ. J. Nat. Sci. 15, 335–339 (2010). https://doi.org/10.1007/s11859-010-0662-2
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DOI: https://doi.org/10.1007/s11859-010-0662-2
Key words
- parallel matched filter
- finite-impulse response (FIR)
- window function
- polyphase filtering
- field programmable gate array