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An asynchronous 32×8-bit multiplier based on LDCVSPG logic

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Wuhan University Journal of Natural Sciences

Abstract

An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate (LDCVSPG) logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation (CSMC’s) 0.6 μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.

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Authors and Affiliations

  1. School of Electronic, Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, 200030, China

    Zhong Xiongguang & Rong Mengtian

Authors
  1. Zhong Xiongguang
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  2. Rong Mengtian
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Corresponding author

Correspondence to Rong Mengtian.

Additional information

Foundation item: Supported by the National High Technology Research and Development Program of China (2001AA141040)

Biography: ZHONG Xiongguang(1976–), male, Ph.D. candidate,research direction: asynchronous processor design,SoC design methodology.

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Zhong, X., Rong, M. An asynchronous 32×8-bit multiplier based on LDCVSPG logic. Wuhan Univ. J. of Nat. Sci. 12, 294–298 (2007). https://doi.org/10.1007/s11859-006-0045-x

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  • DOI: https://doi.org/10.1007/s11859-006-0045-x

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