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Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias

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Abstract

During service, through-silicon vias (TSVs) in vertically stacked-die microelectronic packages are subjected to both thermo-mechanical cycling as well as electromigration. The disparate properties of Cu-filled TSVs and the Si chip induce substantial residual stresses in both components, as well as at the interface. These stresses may drive interfacial sliding with the interface serving as a rapid diffusion path, resulting in significant interfacial strain incompatibilities. In addition, by acting as short-circuit paths for diffusion, the interfaces may carry significant electromigration fluxes, further exacerbating interfacial sliding. The results of recent experiments and modeling are presented to illustrate these effects, and related reliability issues are discussed.

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Authors and Affiliations

  1. School of Mechanical and Materials Engineering, Washington State University, Pullman, WA, 99163, USA

    I. Dutta & P. Kumar

  2. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332, USA

    M. S. Bakir

Authors
  1. I. Dutta
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  2. P. Kumar
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  3. M. S. Bakir
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Correspondence to I. Dutta.

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Dutta, I., Kumar, P. & Bakir, M.S. Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias. JOM 63, 70–77 (2011). https://doi.org/10.1007/s11837-011-0179-y

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  • DOI: https://doi.org/10.1007/s11837-011-0179-y

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