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An overview of Pb-free, flip-chip wafer-bumping technologies

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Abstract

To meet the European Union Restriction of Hazardous Substances requirements and the continuing demand for lower costs, finer pitch, and high-reliability flip-chip packaging structures, considerable work is going on in the electronic industry to develop leadfree solutions for flip-chip technology. In this paper, various solder-bumping technologies developed for flip-chip applications are reviewed with an emphasis on a new wafer-bumping technology called C4NP (Controlled-Collapse-Chip-Connect New Process). Several inherent advantages of C4NP technology are discussed over other technologies. This paper will also discuss the recent development and implementation of lead-free C4 interconnections for 300 mm wafers demonstrated at IBM. In addition, some metallurgical considerations associated with C4NP technology are discussed.

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Authors and Affiliations

  1. IBM T.J. Watson Research Center, Yorktown Heights, New York, 10598, USA

    Sung K. Kang, Peter Gruber & Da-Yuan Shih

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  1. Sung K. Kang
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  2. Peter Gruber
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  3. Da-Yuan Shih
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Correspondence to Sung K. Kang.

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Kang, S.K., Gruber, P. & Shih, DY. An overview of Pb-free, flip-chip wafer-bumping technologies. JOM 60, 66–70 (2008). https://doi.org/10.1007/s11837-008-0075-2

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  • DOI: https://doi.org/10.1007/s11837-008-0075-2

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