Journal of Central South University

, Volume 21, Issue 8, pp 3205–3213 | Cite as

NAND flash service lifetime estimate with recovery effect and retention time relaxation

  • Kai Bu (步凯)
  • Yi-ran Chen (陈怡然)
  • Hui Xu (徐晖)
  • Wei Yi (易伟)
  • Qi-you Xie (谢启友)


A service life model of NAND flash and threshold voltage shift process is proposed to calculate the service life and endurance. The relationships among achievable program/erase (P/E) cycles, recovery time, bad block rate and storage time are analyzed. The achievable endurance and service life of a NAND flash are evaluated based on a flash cell degradation and recovery model by varying recovery time, badblock rate, and storage time. It is proposed to improve the service lifetime of solid state disk by both relaxing the bad block rate limitation and retention time while extending the recovery time. The results indicate that endurance can be improved by 17 times if the storage time guarantee is reduced from 10 a to 1 a with 105 s recovery time inserted between cycles.

Key words

NAND flash endurance retention recovery effect program/erase (P/E) cycle 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    GRUPP L M, CAULFIELD A M, COBURN J, SWANSON S, YAAKOBI E, SIEGEL P H, WOLF J K. Characterizing flash memory: Anomalies, observations, and applications [C]// Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. New York: ACM, 2009: 24–33.CrossRefGoogle Scholar
  2. [2]
    JEDEC Solid State Technology Association. JESD218A: JEDEC solid-state drive (SSD) requirements and endurance test method [R]. Arlington: JEDEC, 2011.Google Scholar
  3. [3]
    PABLO A Z. Taking consumer MLC to extreme endurance [R]. Santa Clara: Flash Memory Summit, 2012.Google Scholar
  4. [4]
    DONG Gui-qiang, PAN Yang-yang, XIE N, VARANASI C, ZHANG Tong. Estimating information-theoretical NAND flash memory storage capacity and its implication to memory system design space exploration [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(9): 1705–1714.CrossRefGoogle Scholar
  5. [5]
    WANG Chun-dong, WONG Weng-Fai. Extending the lifetime of NAND flash memory by salvaging bad blocks [C]// Proceedings of the Conference on Design, Automation and Test in Europe. San Jose: EDA Consortium, 2012: 260–263.Google Scholar
  6. [6]
    SMART Storage Systems: Why and how of ssd over provisioning [R]. Newark: SMART Storage Systems, 2012: 8–10.Google Scholar
  7. [7]
    SUN Hai-rong, GRAYSON P, WOOD B. Quantifying reliability of solid-state storage from multiple aspects [C]// 27th IEEE (MSST 2011) Symposium on Massive Storage Systems and Technologies and Co-located Events. Denver: MSST Committee, 2011: 234–240.Google Scholar
  8. [8]
    GHIDINI G. Charge-related phenomena and reliability of non-volatile memories [J]. Microelectronics Reliability, 2012, 52(9): 1876–1882.CrossRefGoogle Scholar
  9. [9]
    MIELKE N, BELGAL H, KALASTIRSKY I, PRANAV K, KURTZ A, MENG Q R, RIGHOS N, WU J. Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling [J]. IEEE Transactions on Device and Materials Reliability, 2004, 4(3): 335–344.CrossRefGoogle Scholar
  10. [10]
    YANG H, KIM H, PARK S, CHOI J K, KIM C, PARK M. Reliability issues and models of sub-90nm NAND flash memory cells [C]// International conference on Solid-State and Integrated Circuit Technology, Piscataway: IEEE, 2006: 760–762.Google Scholar
  11. [11]
    LEE J D, CHOI J H, PARK D, KIM K, CO S E, DO G. Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells [J]. IEEE Transactions on Device Material Reliability, 2004, 4(1): 110–117.CrossRefGoogle Scholar
  12. [12]
    JEDEC Solid State Technology Association. JEDEC47I: Stress-test-driven qualification of integrated circuits [R]. Arlington: JEDEC, 2012.Google Scholar
  13. [13]
    MOHAN V, SIDDIQUA T, GURUMURTHI S, MIRCEA R. How I learned to stop worrying and love flash endurance [C]// HotStorage’10 Proceedings of the 2nd USENIX Conference on Hot Topics in Storage and File Systems. Berkeley: USENIX Association, 2010: 23–28.Google Scholar
  14. [14]
    CHEN J J, MIELKE N R, HU K C. Flash memory reliability, nonvolatile memory technologies with emphasis on flash: A comprehensive guide to understanding and using flash memory devices [M]. Hoboken: Wiley Interscience, 2010: 32–34.Google Scholar
  15. [15]
    MIELKE N, BELGAL H, FAZIO A, MENG Q, RIGHOS N. Recovery effects in the distributed cycling of flash memories [C]// Proceedings of IEEE International Reliability Physics Symposium. Piscataway: IEEE, 2006: 29–35.Google Scholar
  16. [16]
    MICCOLI C, COMPAGNONI C, BELTRAMI S, SPINELLI A, VISCONTI A. Threshold-voltage instability due to damage recovery in nanoscale nand flash memories [J]. IEEE Transactions on Electron Devices, 2011, 58(8): 2406–2414.CrossRefGoogle Scholar
  17. [17]
    LIU Ren-shuo, YANG Chia-lin, WU Wei. Optimizing NAND flash-based SSDs via retention relaxation [C]// Proceedings of the 10th USENIX conference on File and Storage Technologies. Berkeley: USENIX Association, 2012: 94–107.Google Scholar

Copyright information

© Central South University Press and Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Kai Bu (步凯)
    • 1
    • 2
  • Yi-ran Chen (陈怡然)
    • 1
  • Hui Xu (徐晖)
    • 2
  • Wei Yi (易伟)
    • 2
  • Qi-you Xie (谢启友)
    • 2
  1. 1.Department of Electrical and Computer EngineeringUniversity of PittsburghPittsburghUSA
  2. 2.School of Electronic Science and EngineeringNational University of Defense TechnologyChangshaChina

Personalised recommendations