Abstract
In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code (ECC) along with scrubbing is an efficient method for protecting memories against these errors. However, the latency of coding circuits brings speed penalties in high performance applications. This paper proposed a “bit bypassing” ECC protected memory by buffering the encoded data and adding an identifying address for the input data. The proposed memory design has been fabricated on a 130 nm CMOS process. According to the measurement, the proposed scheme only gives the minimum delay overhead of 22.6%, compared with other corresponding memories. Furthermore, heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.
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References
Soonyoung Lee, Sang Hoon Jeon, and Sanghyeon Baeg. Memory reliability analysis for multiple block effect of soft errors. IEEE Transactions on Nuclear Science, 60(2013)2, 1384–1389.
Onur Mutlu. Memory scaling: a systems architecture perspective. 2013 5th IEEE International Memory Workshop, Monlterey, USA, May 26–29, 2013, 288–292.
Jing Guo, Liyi Xiao, Zhigang Mao, and Qiang Zhao. Enhanced memory reliability against multiple cell upsets using decimal matrix code. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2014)1, 127–135.
Costas Argyrides, Pedro Reviriego, and Juan Antonio Maestro. Using single error correction codes to protect against isolated defects and soft errors. IEEE Transactions on Reliability, 62(2013)1, 238–243.
Xiaoxuan She, N. Li, and D. Waileen Jensen. SEU tolerant memory using error correction code. IEEE Transaction of Nuclear Science, 59(2012)1, 205–210.
Valentin Gherman, Samuel Evain, Fabrice Auzanneau, and Yannick Bonhomme. Programmable extended SEC-DED codes for memory errors. 2011 20th IEEE VLSI Test Symposium, Laguna Cliffs Marriott Resort and Spa Dana Point, USA, May 1–5, 2011, 140–145.
Juan Antonio Maestro, and Pedro Reviriego. Fault tolerant single error correction encoders, Journal of Electronic Testing, 27(2011)2, 215–218.
Altera Corporation, Stratix III device handbook, San Jose, CA, USA, 2011, 40–41.
Altera Corporation, Stratix IV device handbook, San Jose, CA, USA, 2011, 63–64.
Altera Corporation, Stratix V device handbook, San Jose, CA, USA, 2011, 48–49.
Manuel Cabanas-Holmen, Ethan H. Cannon, Tony Amort, et al.. Predicting the single-event error rate of a radiation hardened by design microprocessor. IEEE Transactions of Nuclear Science, 58(2011)6, 2726–2732.
M. Ceschia, M. Violante, and M. S Reorda. Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs. IEEE Transactions on Nuclear Science, 50(2003)6, 134–139.
Karl C. Mohr and Lawrence T. Clark. Delay and area efficient first-level cache soft error detection and correction. International Conference on Computer Design, San Jose, CA, USA, October 1–4, 2006, 28–33.
K. C. Mohr, G. Samson, and L. T. Clark. A radiation hardened by design register file with light weight error detection and correction. IEEE Transactions on Nuclear Science, 54(2007)4, 1335–1342.
F. Ricci. A 1.5 GHz 90nm embedded microprocessor core. IEEE Symposium on VLSI Circuit Technology, Kyoto, Japan, June. 16–18, 2005, 12–15.
Alexander Brant, Ameer Abdelhadi, Aaron Severance, et al.. Pipeline frequency boosting: hiding dual-ported block RAM latency using intentional clock skew. 2012 International Conference on Field-Programmable Technology (FPT), Seoul, Korea, December 10–12, 2012, 235–238.
Cui Yuanyuan, Lou Mian, Xiao Jianqing, and Zhang Xunjing. Research and implementation of SEC-DED hamming code algorithm. 2013 IEEE Region 10 Conference (TECON), Xi’an, China, October 22–25, 2013, 35–40.
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Supported by the National Science and Technology Major Project of China (No. 2013ZX03006004).
Communication author: Yang Haigang, born in 1960, male, Doctor Degree.
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Zhi, T., Yang, H., Cai, G. et al. Eliminating speed penalties in ECC protected memory designs using “bit bypassing” techniques. J. Electron.(China) 31, 290–297 (2014). https://doi.org/10.1007/s11767-014-4040-7
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DOI: https://doi.org/10.1007/s11767-014-4040-7