Abstract
Field Programmable Gate Arrays (FPGAs) offer high capability in implementing of complex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets (SEUs). To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided. In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA. Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.
Similar content being viewed by others
References
P. K. Samudrala, J. Ramos, and S. Katkoori. Selective triple modular redundancy (STMR) based singleevent upset (SEU) tolerant synthesis for FPGAs. IEEE Transactions on Nuclear Science, 51(2004)5, 2957–2969.
L. Sterpone and M. Violante. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. IEEE Transactions on Nuclear Science, 52 (2005)5, 1545–1549.
L. Sterpone and M. Violante. A new reliabilityoriented place and route algorithm for SRAM-based FPGAs. IEEE Transactions on Computers, 55(2006)6, 732–744.
B. Pratt, M. Caffrey, J. F. Carroll, P. Graham, K. Morgan, and M. Wirthlin. Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Transactions on Nuclear Science, 55(2008)4, 2274–2280.
K. Xing, J. Yang, C. Zhang, and W. He. Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA. Science China Technological Sciences, 54(2011)10, 2657–2664.
M. Portela-Garcia, A. Lindoso, L. Entrena, M. Garcia-Valdera, C. Lopez-Ongil, N. Marroni, B. Pianta, L. B. Poehls, and F. Vargas. Evaluating the effectiveness of a software-based technique under SEEs using FPGA-based fault injection approach. Journal of Electronic Testing, 27(2012)5, 627–633.
A. Ejlali and S. Ghassem Miremadi. FPGA-based fault injection into switch-level models. Microprocessors and Microsystems, 28(2004)5/6, 317–327.
H. R. Zarandi and S. G. Miremadi. Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. Microelectronics Reliability, 47 (2007)2/3, 461–470.
L. Sterpone and M. Violante. A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs. IEEE Transactions on Nuclear Science, 52 (2005)6, 2217–2223.
L.-O. Celia, G.-V. Mario, P.-G. Marta, and E. Luis. Autonomous fault emulation: a new FPGA based acceleration system for hardness evaluation. IEEE Transactions on Nuclear Science, 54(2007)1, 252–261.
P. S. Ostler, M. P. Caffrey, D. S. Gibelyou, P. S. Graham, K. S. Morgan, B. H. Pratt, H. M. Quinn, and M. J. Wirthlin. SRAM FPGA reliability analysis for harsh radiation environments. IEEE Transactions on Nuclear Science, 56(2009)6, 3519–3526.
P. Schumacher. WP414: SEU emulation environment. Xilinx Corp. technical document, San Jose, CA, USA, Xilinx Inc., 2012.
Brendan Bridgford, Carl Carmichael, and C. W. Tseng. Single event upset mitigation selection guide. Xilinx Corp. application document, San Jose, CA, USA, Xilinx Inc., 2008.
K. Chapman. SEU strategies for Virtex-5 devices. Xilinx Corp. technical document, San Jose, CA, USA, Xilinx Inc., 2011.
U. Legat, A. Biasizzo, and F. Novak. A compact AES core with on-line error-detection for FPGA applications with modest hardware resources. Microprocessors and Microsystems, 35(2011)4, 405–416.
R. L. Shuler, B. L. Bhuva, P. M. O’Neill, J. W. Gambles, and S. Rezgui. Comparison of dual-rail and TMR logic cost effectiveness and suitability for FPGAs with reconfigurable SEU tolerance. IEEE Transactions on Nuclear Science, 56(2009)1, 214–219.
K. S. Morgan, D. L. McMurtrey, B. H. Pratt, and M. J. Wirthlin. A comparison of TMR with alternative fault-tolerant design techniques for FPGAs. IEEE Transactions on Nuclear Science, 54(2007)6, 2065–2072.
R. O. Gosheblagh and K. Mohammadi. Designing and implementing a reliable thermal monitoring system based on 1-wire protocol on FPGA for a LEO satellite. Turkish Journal of Electrical Engineering & Computer Sciences, DOI: 10.3906/elk-1301-15, 2013.
S. F. Liu, G. Sorrenti, P. Reviriego, F. Casini, J. A. Maestro, and M. Alderighi. Increasing reliability of FPGA-based adaptive equalizers in the presence of single event upsets. IEEE Transactions on Nuclear Science, 58(2011)3, 1072–1077.
M. A. Aguirre, J. N. Tombs, F. Muoz, V. Baena, H. Guzman, J. Napoles, A. Torralba, A. Fernandez-Leon, F. Tortosa-Lopez, and D. Merodio. Selective protection analysis using a SEU emulator: testing protocol and case study over the Leon2 processor. IEEE Transactions on Nuclear Science, 54(2007)4, 951–956.
U. Legat, A. Biasizzo, and F. Novak. SEU recovery mechanism for SRAM based FPGAs. IEEE Transactions on Nuclear Science, 59(2012)5, 2562–2571.
M. Straka, J. Kastil, Z. Kotasek, and L. Miculka. Fault tolerant system design and SEU injection based testing. Microprocessors and Microsystems, 37(2013)2, 155–173.
E. Johnson, M. Caffrey, P. Graham, N. Rollins, and M. Wirthlin. Accelerator validation of an FPGA SEU simulator. IEEE Transactions on Nuclear Science, 50 (2003)6, 2147–2157.
P. M. -H. Lee and R. Sedaghat. FPGA-based switchlevel fault emulation using module-based dynamic partial reconfiguration. Microelectronics Reliability, 48(2008)10, 1724–1733.
J. M. Mogollon, H. Guzman-Miranda, J. Napoles, J. Barrientos, and M. A. Aguirre. FTUNSHADES2: a novel platform for early evaluation of robustness against SEE. 12th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sevilla, Spain, September 2011, 169–174.
L. Sterpone and M. Violante. A new partial reconfigurationbased fault-injection system to evaluate SEU effects in SRAM-based FPGAs. IEEE Transactions on Nuclear Science, 54(2007)4, 965–970.
A. Rohani and H. G. Kerkhoff. Rapid transient fault insertion in large digital systems. Microprocessors and Microsystems, 37(2013)2, 147–154.
H. M. Quinn, P. S. Graham, M. J. Wirthlin, B. Pratt, K. S. Morgan, M. P. Caffrey, and J. B. Krone. A test methodology for determining space readiness of Xilinx SRAM based FPGA devices and designs. IEEE Transactions on Instrumentation and Measurement, 58(2009)10, 3380–3395.
L. Antoni, R. Leveugle, and B. Feher. Using run-time reconfiguration for fault injection applications. IEEE Transactions on Instrumentation and Measurement, 52(2003)5, 1468–1473.
C. I. Underwood. Observations of radiation in the space radiation environment and its effect on commercial off-the-shelf electronics in low-Earth orbit. Philosophical Transactions of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences, 361(2003)1802, 193–197.
W. Lu and M. Radetzki. Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Microprocessors and Microsystems, 37(2013)2, 115–128.
S. Misera, H. T. Vierhaus, and A. Sieber. Simulated fault injections and their acceleration in SystemC. Microprocessors and Microsystems, 32(2008)5/6, 270–278.
O. Goloubeva, M. Rebaudengo, O. Goloubeva, and M. Rebaudengo. Software-implemented Hardware Fault Tolerance. Springer, Berlin, Germany, 2006, 18–120.
B. Dutton, M. Ali, C. Stroud, and J. Sunwoo. Embedded processor based fault injection and SEU emulation for FPGAs. Proceedings of the International Conference on Embedded Systems and Applications, Las Vegas, Nevada, USA, July 2009, 183–189.
L. Sterpone, M. Violante, R. H. Sorensen, D. Merodio, F. Sturesson, R. Weigand, and S. Mattsson. Experimental validation of a tool for predicting the effects of soft errors in SRAM based FPGAs. IEEE Transactions on Nuclear Science, 54(2007)6, 2576–2583.
M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, D. M. Codinachs, S. Pastore, C. Poivey, G. R. Sechi, G. Sorrenti, and R. Weigand. Experimental validation of fault injection analyses by the FLIPPER tool. IEEE Transactions on Nuclear Science, 57(2010)4, 2129–2134.
J. Tombs and M. A. Aguirre. FT-UNSHADES tool. Eurpe Space Agency Microelectronics Day, 2004.
L. Dongwoo and N. Jongwhoa. A novel simulation fault injection method for dependability analysis. IEEE Design & Test of Computers, 26(2009)6, 50–61.
M. Alderighi, F. Casini, M. Citterio, S. D’Angelo, M. Mancini, S. Pastore, G. R. Sechi, and G. Sorrenti. Using FLIPPER to predict proton irradiation results for VIRTEX 2 devices: a case study. IEEE Transactions on Nuclear Science, 56(2009)4, 2103–2110.
UG071: Virtex-4 FPGA configuration user guide. Xilinx technical documents, San Jose, CA, USA, Xilinx Inc.
S. Schirrmann. User manual for Zefant-nanov4. Simplesolutions Corp. technical document, 2011.
UG632: PlanAhead user guide. Xilinx technical documents, San Jose, CA, USA, Xilinx Inc., 2009.
Author information
Authors and Affiliations
Corresponding author
About this article
Cite this article
Gosheblagh, R.O., Mohammadi, K. New approach to emulate SEU faults on SRAM based FPGAS. J. Electron.(China) 31, 68–77 (2014). https://doi.org/10.1007/s11767-014-3122-x
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11767-014-3122-x
Key words
- Field Programmable Gate Arrays (FPGAs)
- Single-Event Upset (SEU) fault injection
- Soft-core
- Space radiation effects