Skip to main content
Log in

Ctuning: A reuse distance based cache performance tuning tool

  • Published:
Journal of Electronics (China)

Abstract

Cache performance tuning tools are conducive to develop program with good locality and fully use cache to decrease the influence caused by speed gap between processor and memory. This paper introduces the design and implementation of a cache performance tuning tool named CTuning, which employs a source level instrumentation method to gather program data access information, and uses a limited reuse distance model to analyze cache behavior. Experiments on 183.equake improve average performance more than 6% and show that CTuning is proficient not only in locating cache performance bottlenecks to guide manual code transformation, but also in analyzing cache behavior relationship among variables, thus to direct manual data reorganization.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. K. Beyls and E. D’Hollander. Intermediately executed code is the key to find refactorings that improve temporal data locality. In Proceedings of the 3rd Conference on Computing Frontiers, Ischia, Italy, 2006, 373–382.

  2. X. Shen, Y. Zhong, and C. Ding. Predicting locality phases for dynamic memory optimization. Journal of Parallel and Distributed Computing, 67(2007)7, 83–796.

    Article  Google Scholar 

  3. Y. Zhong, M. Orlovich, X. Shen, and C. Ding. Array regrouping and structure splitting using whole-program reference affinity. In Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation, Washington D.C., June 2004, 255–266.

  4. K. Beyls, E. D’Hollander, and F. Vandeputte. RDVIS: A tool that visualizes the causes of low locality and hints program optimizations. In ICCS’2005, Lecture Notes in Computer Science. Atlanta, USA, 2005. Vol. 3515, 166–173.

    Google Scholar 

  5. R. A. Sugumar and S. G. Abraham. Efficient simulation of multiple cache configurations using binomial trees. Technical Report CSE-TR-111-91, University of Michigan, 1991.

  6. X. Fu, Y. Zhang, and Y. Chen. Data-layout optimization using reuse distance distribution. The International Workshop on Embedded Software Optimization, Lecture Notes in Computer Science. Seoul, Korea, August 2006, Vol.4097, 858–867.

  7. J. Marathe, F. Mueller, T. Mohan, et al. METRIC: Memory tracing via dynamic binary rewriting to identify cache inefficiencies. ACM Transactions on Programming Languages and Systems (TOPLAS), 29 (2007)2, 1–36.

    Article  Google Scholar 

  8. J. Weinberg and A. Edward Snavely. Accurate memory signatures and synthetic address traces for HPC applications. In Proceedings of the 22nd Annual International Conference on Supercomputing (ICS), Island of Kos, Greece, June 2008, 36–45.

  9. E. Raman, R. Hundt, and S. Mannarswamy. Structure layout optimization for multithreaded programs. In Proceedings of the International Symposium on Code Generation and Optimization (CGO), San Jose, California, March 2007, 271–282.

  10. R. L. Mattson, J. Gecsei, D. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM System Journal, 9(1970)2, 78–117.

    Article  Google Scholar 

  11. S. Viswanadha, et al. Java Compiler Compiler (JavaCC)[EB/OL]. 2008-12-11.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Xiong Fu.

Additional information

Sponsored by the National Natural Science Foundation of China (No.60573141, 60773041), National 863 High Technology Research Program of China (No.2007AA01Z404, 2007AA01Z478), High Technology Research Programme of Jiangsu Province (No.BG2006001), Key Laboratory of Information Technology Processing of Jiangsu Province (kjs06006), and Project of NJUPT (NY207135).

Communication author: Fu Xiong, born in 1979, male, Ph.D.

About this article

Cite this article

Fu, X., Wang, R. Ctuning: A reuse distance based cache performance tuning tool. J. Electron.(China) 26, 517–524 (2009). https://doi.org/10.1007/s11767-008-0023-x

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11767-008-0023-x

Key words

CLC index

Navigation