Abstract
A Single-Buffered (SB) router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued (CIOQ) router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-Performance Networking Group (HPNG) of Stanford University, along with two promising designs of SB routers: one of which was Parallel Shared Memory (PSM) router and the other was Distributed Shared Memory (DSM) router. Admittedly, the work of HPNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm (CMMA) which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued (VOIQ) router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and communication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router (NDSC® SR1880-T™ series) are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now.
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References
N. McKeown, V. Anantharam, J. Walrand, et al. Achieving 100% throughput in an input-queued switch. IEEE Trans. on Commun., 47(1999)8, 1260–1267.
S. Chuang, A. Goel, N. McKeown. Matching output queueing with a combined input/output-queued switch. IEEE J. on Sel. Areas in Commun., 17(1999)6, 1030–1039.
J. Dai, B. Prabhakar. The throughput of data switches with and without speedup. In Proc. of IEEE INFOCOM’00, Tel Aviv, Israel, March 26–30, 2000, 556–564.
A. Charny, P. Krishna, N. S. Patel, R. Simcoe. Algorithms for providing bandwidth and delay guarantees in input-buffered crossbars with speedup. 6th International Workshop on Quality of Service (IWQoS’98), Napa, CA, May 18–20, 1998, 235–244.
A. Francini, F. M. Chiussi. Providing QoS guarantees to unicast and multicast flows in multistage packet switches. IEEE J. on Sel. Areas in Commun., 20 (2002)8, 1589–1601.
F. M. Chiussi, A. Francini. Scalable electronic packet switches. IEEE J. on Sel. Areas in Commun., 21(2003)4, 486–500.
S. Iyer, R. Zhang, N. McKeown. Routers with a single stage of buffering. In Proc. of ACM SIGCOMM’ 02, Pittsburgh, US, August 19–23, 2002, 251–264.
High-Performance Networking Group. Available at: http://yuba.stanford.edu/.
T. Chaney, J. A. Fingerhut, M. Flucke, J. Turner. Design of a gigabit ATM switching system. Technical Report WUCS-96-07, Computer Science Department, Washington University, St. Louis, Missouri, Feb. 1996.
P. S. Sindhu, R. K. Anand, D. C. Ferguson, B. O. Liencres. High speed switching device. United States Patent No. 5905725, 1999.
A. K. Parekh, R. G. Gallager. A generalized processor sharing approach to flow control in integrated services networks: The single node case. IEEE/ACM Trans. on Networking, 1(1993)3, 344–357.
J. C. R. Bennett, H. Zhang. WF2Q: Worst-case fair weighted fair queueing. In Proc. of INFOCOM’96, San Francisco, March 24–28, 1996, 120–128.
J. C. R. Bennett, H. Zhang. Hierarchical packet fair queueing algorithms. IEEE/ACM Trans. on Networking, 5(1997)5, 675–689.
I. Stoica, H. Abdel-Wahab. Earliest eligible virtual deadline first: A flexible and accurate mechanism for proportional share resource allocation. Technical Report TR-95-22, Old Dominion University, November 1995.
Wang Binqiang. NDSC® SR1880-T™ router. Technical report, Available at: http://www.ndsc.com.cn/ (in Chinese).
汪 斌强. NDSC® SRt880-T™ 路由器. 技术报告, 参见: http://www.ndsc.ndsc.com.cn/.
Test Specification for High-End Router. YD/T 1156-2001, China Ministry of Information Industry (MII), Sep., 2001 (in Chinese).
路由器测试规范-高端路由器. YD/T 1156-2001, 信息产业部, 2001 年 9 月.
Router Equipment Technical Specification-High End Router. YD/T 1097-2001, China Ministry of Information Industry (MII), Feb., 2001 (in Chinese).
路由器设备技术规范-高端路由器, YD/T 1097-2001, 信息产业部, 2001 年 2 月
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Supported by the National High-Tech Research and Development Program of China (863 Program) (2003AA103510, 2004AA103130, 2005AA121210).
Communication author: Hu Ximing, born in 1978, male, Ph.D., engineer. National Digital Switching System Engineering & Technological R&D Center (NDSC), Zhengzhou 450002, China.
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Hu, X., Qu, J., Wang, B. et al. Design and implementation of Single-Buffered routers. J. of Electron.(China) 24, 470–476 (2007). https://doi.org/10.1007/s11767-005-0244-5
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DOI: https://doi.org/10.1007/s11767-005-0244-5
Key words
- Single-Buffered (SB) router
- Distributed Shared Memory (DSM)
- Parallel Shared Memory (PSM)
- Virtual Output and Input Queued (VOIQ)
- NDSC® SR1880-T™ router