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Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuit

  • Published:
Journal of Electronics (China)

Abstract

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25µm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

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Authors and Affiliations

  1. Institute of Circuits and Systems, Ningbo University, Ningbo, 315211, China

    Wang Pengjun (male, doctor, associate professor) & Yu Junjun

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  1. Wang Pengjun
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  2. Yu Junjun
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Correspondence to Wang Pengjun.

Additional information

Supported by the National Natural Science Foundation of China (No. 60273093), the Natural Science Foundation of Zhejinag Province (No. Y104135) and the Student Scientific Research Foundation of Ningbo university (No.C38).

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Wang, P., Yu, J. Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuit. J. of Electron.(China) 24, 225–231 (2007). https://doi.org/10.1007/s11767-005-0170-2

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  • DOI: https://doi.org/10.1007/s11767-005-0170-2

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