Abstract
Single-Pole Double-Throw (SPDT) broadband switch has been designed in a 0.25µm Complementary Metal Oxide Semiconductor (CMOS) process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances (GSR) on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC (Direct Current) to 1GHz exhibits 55dB and insertion loss lower than 2.1dB.
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Partially supported by the National Natural Science Foundation of China (No.60501012).
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Han, L., Yang, T., Xie, J. et al. A design of 0.25μm CMOS switch. J. of Electron.(China) 23, 745–747 (2006). https://doi.org/10.1007/s11767-005-0008-y
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DOI: https://doi.org/10.1007/s11767-005-0008-y