Skip to main content
SpringerLink
Log in

Forward gated-diode method for directly measuring stress-induced interface traps in NMOSFET/SOI

  • Letters
  • Published:
Journal of Electronics (China)

Abstract

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of ΔN it∼t 0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

References

  1. A. Pacelli, A. L. Lacaita, S. Villa, Reliable extraction of MOS interface traps from low frequency CV measurements, IEEE EDL, EDL-19(1998)5, 148–150.

    Google Scholar 

  2. C. H. Ling, S. E. Tan, D. S. Ang, A study of hot carrier degradation on NMOSFET’s by gate capacitance and charge pumping current, IEEE Trans. on ED, ED-42(1995)2, 1321–1328.

    Google Scholar 

  3. He Jin, Huang Aihua, et al., Forward gated-diode R-G current method: A simple novel technique for characterizing the lateral lightly doping region of LDD MOSFET’s, Journal of Electronics(China), 18(2001)2, 188–192.

    Google Scholar 

  4. He Jin, Zhang Xing, et al., Numerical analysis of characterizing back interface traps of SOI devices by R-G Current, Chinese Journal of Semiconductors, 21(2000)12, 1145–1152.

    Google Scholar 

  5. X. J. Zhao, Dimitris E. Ioannou, A sensitive tool for characterizing the buried Si-SiO2 interface, Proceeding of 1999 IEEE International SOI Conference, Sonoma County, USA, Oct. 1999, 52–53.

  6. T. Ernst, S. Cristoloveanu, A. Vandooren, et al., Recombination current modeling and carrier lifetime extraction in dual-gated fully-depleted SOI devices, IEEE Trans. on ED, ED-46(1999)7, 1503–1509.

    Article  Google Scholar 

  7. C. H. Ling, B. P. Seah, G. S. Samudra, C. H. Gan, Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance, IEEE Trans. on ED, ED-42(1995)2, 928–934.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Microelectronics, Peking University, 100871, Beijing

    Huang Aihua, He Jin, Zhang Xing, Huang Ru & Wang Yangyuan

  2. Digital DNA Lab, SPS, Motorola Electronics, Ltd., 100022, Beijing

    Yu Shan & Jia Lin

Authors
  1. Huang Aihua
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. He Jin
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Zhang Xing
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Huang Ru
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Wang Yangyuan
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Yu Shan
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Jia Lin
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

Sponsored by Motorola-Peking University Joint Project. Contract No.: MSPSDDLCHINA-0004

About this article

Cite this article

Huang, A., He, J., Zhang, X. et al. Forward gated-diode method for directly measuring stress-induced interface traps in NMOSFET/SOI. J. of Electron.(China) 19, 104–107 (2002). https://doi.org/10.1007/s11767-002-0019-x

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11767-002-0019-x

Key words

Search

Navigation