Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋th) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.
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Negrini R, Sami M G, Stefanelli R. Fault tolerance through reconfiguration in VLSI and WSI arrays. The MIT Press, 1989
Mangir T E, Avizienis A. Fault-tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI design. IEEE Trans. on Computers, 1982, 31(7): 609–615
Greene J W, Gamal A E. Configuration of VLSI array in the presence of defects. J. ACM, 1984, 31(4): 694–717
Sami M, Stefanelli R. Reconfigurable architectures for VLSI processing array. Proceedings of the IEEE, 1986, 74(5): 712–722
Negrini R, Sami M G, Stefanelli R. Fault Tolerance Through Reconfiguration in VLSI and WSI arrays. The MIT Press, 1989
Lam C W H, Li H F, Jakakumar R. A study of two approaches for reconfiguring fault-tolerant systoric array. IEEE Trans. on Computers, 1989, 38(6): 833–844
Koren I, Singh A D. Fault tolerance in VLSI circuits. Computer, 1990, 23(7): 73–83
Chen Y Y, Upadhyaya S J, Cheng C H. A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors. IEEE Trans. on Computers, 1997, 46(12): 1363–1371
Kuo S Y, Fuchs W K. Efficient spare allocation for reconfigurable arrays. IEEE Design and Test, 1987, 4(7): 24–31
Wey C L, Lombardi F. On the repair of redundant RAM’s. IEEE Trans. on Computer-Aided Design, 1987, CAD-6(2): 222–231
Tsuda N. Reconfigurable mesh-connected processor arrays using rowcolumn bypassing and direct replacement. In: Proceedings of International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000, 24–29
Takanami I. Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement. In: Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 2001, 134–142
Kuo S Y, Chen I Y. Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. IEEE Trans. on Computer-Aided Design, 1992, 11(10): 1289–1300
Low C P, Leong H W. On the reconfiguration of degradable VLSI/WSI arrays. IEEE Trans. on Computer-Aided Design of integrated circuits and systems, 1997, 16(10): 1213–1221
Low C P. An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. on Computers, 2000, 49(6): 553–559
Wu J G, Srikanthan T. Accelerating reconfiguration of degradable VLSI arrays. IEE Proceedings, Circuits, Devices and Systems, 2006, 153(4): 383–389
Fukushi M, Fukushima Y, Horiguchi S. A genetic approach for the reconfiguration of degradable processor arrays. In: Proceedings of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005, 63–71
Wu J G, Srikanthan T. Reconfiguration Algorithms for Power Efficient VLSI subarrays with 4-port Switches. IEEE Trans. on Computers, 2006, 55(3): 243–253
Wu J G, Srikanthan T. Integrated row and column re-routing for reconfiguration of VLSI arrays with 4-port switches. IEEE Trans. on Computers, 2007, 56(10): 1387–1400
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Wu, J., Srikanthan, T. & Wang, K. Minimizing interconnect length on reconfigurable meshes. Front. Comput. Sci. China 3, 315–321 (2009). https://doi.org/10.1007/s11704-009-0032-4
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