Skip to main content
Log in

Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications

  • Topical Collection: Low-Energy Digital Devices and Computing 2023
  • Published:
Journal of Electronic Materials Aims and scope Submit manuscript

Abstract

This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. L. Bisdounis, D. Gouvetas, and O. Koufopavlou, A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits. Int. J. Electron. 84, 599–613 (1998).

    Article  Google Scholar 

  2. Kwon, O.-H. A Boolean extraction technique for multiple-level logic optimization. in 2003 IEEE International symposium on circuits and systems (ISCAS), vol. 4, IV–IV (IEEE, 2003).

  3. R. Uma, 4-bit fast adder design: topology and layout with self-resetting logic for low power VLSI circuits”. Int. J. Adv. Eng. Sci. Technol. 7, 197–205 (2011).

    Google Scholar 

  4. R. Uma and P. Dhavachelvan, Analysis on impact of behavioral modeling in performance of synthesis process. in Advances in Computing and Information Technology: Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India-Volume 3, 593–602 (Springer, 2013).

  5. L. Chua, Memristor-the missing circuit element. IEEE Trans. Circuit Theory 18, 507–519 (1971).

    Article  Google Scholar 

  6. M. Shahsavari and P. Boulet, Memristor nanodevice for unconventional computing: review and applications. arXiv preprint arXiv:1703.00331 (2017).

  7. C. Chinmay, M. Kenchannavar, A. Tejaswini, and B. Kariyappa, Vteam model based in-memory computation using memristors. Int. J. Innov. Technol. Explor. Eng. 9, 3426–3432 (2019).

    Article  Google Scholar 

  8. S. Sahoo and S. Prabaharan, Nanoionic memristor equipped arithmetic logic unit using VTEAM model. In 2016 Online International Conference on Green Engineering and Technologies (IC-GET), 1–6 (IEEE, 2016).

  9. S. Kvatinsky, M. Ramadan, E.G. Friedman, and A. Kolodny, VTEAM: A general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs 62, 786–790 (2015).

    Google Scholar 

  10. Hussain, S. A., Bevara, V., Sanki, P. K. et al. A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications. In 2022 IEEE International Symposium on Smart Electronic Systems (iSES), 631–634 (IEEE, 2022).

  11. A. Jose and K. Jyothisree, 8-bit Arithmetic Logic Unit (ALU) using full swing restored m-GDI technique. in International Conference on Communication, Embedded-VLSI Systems for Electric Vehicle (ICCEVE 2023), vol. 2023, 49–53 (IET, 2023).

  12. N. Subbulakshmi, R. Sravanthi, M. Stalin, T. Swapna, T. Rajesh, and Y. Greeshma, ALUSGDI: low power arithmetic logic unit based sliced processor using GDI and MGDI. Measur.: Sens. 28, 100842 (2023). https://doi.org/10.1016/j.measen.2023.100842.

    Article  Google Scholar 

  13. S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, Team: threshold adaptive memristor model. IEEE Trans. Circ. Syst. I: Regular papers 60, 211–221 (2012).

    Google Scholar 

  14. D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, and Y. Yang, Novel low power full adder cells in 180nm CMOS technology. 430–433 https://doi.org/10.1109/ICIEA.2009.5138242 (2023).

  15. R. Uma and P. Dhavachelvan, Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits. Procedia Technol. 6, 74–81 (2012).

    Article  Google Scholar 

  16. S. Swetha and M.A. Begum, Design of high speed, area optimized and low power arithmetic and logic unit. Adv. Ind. Eng. Manag. 6, 26–31 (2017).

    Google Scholar 

  17. S. Sarkar, H. Chatterjee, P. Saha, and M. Biswas, 8-bit ALU design using m_GDI technique. In 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI) (48184), pp. 17–22 (IEEE, 2020).

  18. S. Sarkar, S. Sarkar, A. Atta, T. Pahari, N. Majumdar, and S. Mondal, 9T and 8T Full Subtractor Design Using Modified GDI and 3T XOR Technique. in Advances in Computer, Communication and Control: Proceedings of ETES 2018, 487–499 (Springer, 2019). https://doi.org/10.1007/978-981-13-3122-0_49.

  19. V.K. Rai and R. Sakthivel, Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor. Int. J. Adv. Technol. Eng. Explor. 8, 1603 (2021).

    Article  Google Scholar 

  20. Akram, S. M., Rani, V. L. & Sailaja, K. Implementation of low leakage and high performance 8-bit ALU for low power digital circuits. Int. J. Comput. Appl. 82 (2013).

  21. Abou Rahal, J. et al. Low power GDI ALU design with mixed logic adder functionality. In 2018 International Conference on IC Design & Technology (ICICDT), pp. 9–12 (IEEE, 2018).

  22. M.A. El-Bendary and M. Ayman, Efficient multiple 4-bit ALU designs for fast computation and reduced area. Circuits Syst. Signal Process. 41, 4671–4691 (2022).

    Article  Google Scholar 

  23. M.A. El-Bendary and F. Amer, Based on FS-GDI approach with 65 nm technology: low power ALU design. Int. J. Electron. 110, 915–933 (2023).

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Pradyut Kumar Sanki.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Hussain, S.A., Prasad V, P.N.S.B.S.V. & Sanki, P.K. Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications. J. Electron. Mater. (2024). https://doi.org/10.1007/s11664-024-11125-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11664-024-11125-6

Keywords

Navigation