Skip to main content
SpringerLink
Log in

Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET)

  • Original Research Article
  • Published:
Journal of Electronic Materials Aims and scope Submit manuscript

Abstract

A partially extended germanium-source double-gate tunnel field-effect transistor (PEGeDG-TFET) utilizes line and point tunneling phenomena to achieve low ambipolar current and high ON-state current. These advantages are accompanied by an exceptionally low OFF-state current (IOFF) and subthreshold swing with resilience against short-channel effects. However, PEGeDG-TFETs face challenges in terms of large variations in IOFF and changes in electrical characteristics with temperature due to the change in the bandgap of semiconductor material. In this article, we explore the temperature-associated variations of a PEGeDG-TFET under the influence of interface trap charges (ITCs) for reliability assessment. Results revealed that the Shockley–Read–Hall phenomenon is dominant at lower gate bias voltage, leading to IOFF degeneration at high temperature. The band-to-band tunneling (BTBT) phenomenon experiences minor variations at higher temperature and gate voltage. Additionally, at high temperature (500 K), it is discovered that the threshold voltage, cut-off frequency, gain–bandwidth product, transconductance–frequency product, intrinsic gain, and transit time decrease, thus limiting the device reliability in the avionics sector where temperatures fall below 410 K with consistent performance of analog/radio-frequency (RF) parameters. This investigation was conducted via simulations on a Silvaco ATLAS simulator considering ITCs and temperature variations.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

Data Availability

No.

References

  1. A. Ionescu and H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). https://doi.org/10.1038/nature10679.

    Article  CAS  PubMed  Google Scholar 

  2. N. Bagga, A. Kumar, and S. Dasgupta, Demonstration of a novel two source region tunnel FET. IEEE Trans. Electron Devices 64(12), 5256–5262 (2017). https://doi.org/10.1109/TED.2017.2759898.

    Article  CAS  Google Scholar 

  3. Dharmender and K. Nigam, Low-K dielectric pocket and workfunction engineering for DC and analog/RF performance improvement in dual material stack gate oxide double gate TFET. SILICON 13, 2347–2356 (2021). https://doi.org/10.1007/s12633-020-00822-6.

    Article  CAS  Google Scholar 

  4. P. Verma, K. Nigam, and S. Kumar, Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET. Appl. Phys. A 128, 955 (2022). https://doi.org/10.1007/s00339-022-06083-x.

    Article  CAS  Google Scholar 

  5. R. Saha, R. Goswami, and D.K. Panda, Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET. Microelectron. J. 130, 105629 (2022). https://doi.org/10.1016/j.mejo.2022.105629.

    Article  CAS  Google Scholar 

  6. H. Liu, L.-A. Yang, Z. Jin, and Y. Hao, An In0.53Ga0.47As/In0.52Al0.48As heterojunction dopingless tunnel FET with a heterogate dielectric for high performance. IEEE Trans. Electron Devices 66(7), 3229–3235 (2019). https://doi.org/10.1109/TED.2019.2916975.

    Article  CAS  Google Scholar 

  7. S. Sahay and M.J. Kumar, Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX. IEEE Trans. Electron Devices 62(11), 3882–3886 (2015). https://doi.org/10.1109/TED.2015.2478955.

    Article  Google Scholar 

  8. J. Bizindavyi, A.S. Verhulst, D. Verreck, B. Sorée, and G. Groeseneken, Large variation in temperature dependence of band-to-band tunneling current in tunnel devices. IEEE Electron Device Lett. 40(11), 1864–1867 (2019). https://doi.org/10.1109/LED.2019.2939668.

    Article  CAS  Google Scholar 

  9. G. Dewey, B. Chun-Kung, J. Boardman, J.M. Fastenau and R. Kotlyar, Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing. In 2011 International electron devices meeting, Washington, DC, USA (2011), pp. 33.6.1–33.6.4. https://doi.org/10.1109/IEDM.2011.6131666

  10. A.M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, and A. Hikavyy, Fabrication and analysis of a Si/ Si0.55 Ge0.45 heterojunction line tunnel FET. IEEE Trans. Electron Devices 61(3), 707–715 (2014). https://doi.org/10.1109/TED.2014.2299337.

    Article  CAS  Google Scholar 

  11. Y. Zhu, D.K. Mohata, S. Datta, and M.K. Hudait, Reliability studies on high-temperature operation of mixed As/Sb staggered gap tunnel FET material and devices. IEEE Trans. Device Mater. Reliab. 14(1), 245–254 (2014). https://doi.org/10.1109/TDMR.2013.2255875.

    Article  CAS  Google Scholar 

  12. P.G. Der Agopian, J.A. Martino, and A. Vandooren, Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electron. 128, 43–47 (2017). https://doi.org/10.1016/j.sse.2016.10.021.

    Article  CAS  Google Scholar 

  13. G. Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zang, H. Zhu, J.-M. Kuo, T. Kosel, M. Wistey, and P. Fay, Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180m at VDS = 0.5 V. In 2012 International electron devices meeting, San Francisco, CA, USA, pp. 32.6.1–32.6.4 (2012). https://doi.org/10.1109/IEDM.2012.6479154

  14. S.A. Loan and M. Rafat, A high-performance inverted-C tunnel junction FET with source-channel overlap pockets. IEEE Trans. Electron Devices 65(2), 763–768 (2018). https://doi.org/10.1109/TED.2017.2783764.

    Article  Google Scholar 

  15. A. Acharya, A.B. Solanki, S. Glass, Q.T. Zhao, and B. Anand, Impact of gate-source overlap on the device/circuit analog performance of Line TFETs. IEEE Trans. Electron Devices 66(9), 4081–4086 (2019). https://doi.org/10.1109/TED.2019.2927001.

    Article  CAS  Google Scholar 

  16. N. Paras, and S.S. Chauhan, Insights into the DC, RF/Analog and linearity performance of vertical tunneling-based TFET for low-power applications. Microelectron. Eng. 216, 111043 (2019). https://doi.org/10.1016/j.mee.2019.111043.

    Article  CAS  Google Scholar 

  17. O. Kr Singh and B. Kaur, Performance investigation of extended vertical double gate tunnel field effect transistor. In: 2021 IEEE International Conference on Technology, Research, and Innovation for Betterment of Society (TRIBES), Raipur, India, pp. 1-6 (2021). https://doi.org/10.1109/TRIBES52498.2021.9751635

  18. Y. Zhang, Tunneling field effect transistor (TFET) with ultra-shallow pockets formed by asymmetric ion implantation and method of making same. U.S. Patent 9 252 250 B2 (2016).

  19. O.K. Singh, V. Dhandapani, and B. Kaur, Partially extended germanium source DG-TFET: design, analysis, and optimization for enhanced digital and analog/RF parameters. SILICON (2022). https://doi.org/10.1007/s12633-022-02112-9.

    Article  PubMed Central  Google Scholar 

  20. T. Joshi, Y. Singh, and B. Singh, Extended-source double-gate tunnel FET with improved DC and analog/RF performance. IEEE Electron Devices 67(4), 1873–1879 (2020). https://doi.org/10.1109/TED.2020.2973353.

    Article  CAS  Google Scholar 

  21. A.E. Islam, Current status of reliability in extended and beyond CMOS devices. IEEE Trans. Device Mater. Reliab. 16(4), 647–666 (2016). https://doi.org/10.1109/TDMR.2014.2348940.

    Article  CAS  Google Scholar 

  22. J. Madan and R. Chaujar, Numerical simulation of N+ source pocket PIN-GAA-tunnel FET: impact of interface trap charges and temperature. IEEE Trans. Electron Devices 64(4), 1482–1488 (2017). https://doi.org/10.1109/TED.2017.2670603.

    Article  Google Scholar 

  23. S. Sharma, R. Basu, and B. Kaur, Interface trap charges associated reliability analysis of Si/Ge heterojunction doping less TFET. IET Circuits Devices Syst. 15(5), 424–433 (2021). https://doi.org/10.1049/cds2.12037.

    Article  Google Scholar 

  24. S. Sharma, R. Basu, and B. Kaur, Temperature analysis of a dopingless TFET considering interface trap charges for enhanced reliability. IEEE Trans. Electron Devices 69(5), 2692–2697 (2022). https://doi.org/10.1109/TED.2022.3156895.

    Article  CAS  Google Scholar 

  25. J. Madan and R. Chaujar, Temperature associated reliability issues of heterogeneous gate dielectric—gate all around—tunnel FET. IEEE Trans. Nanotechnol. 17(1), 41–48 (2018). https://doi.org/10.1109/TNANO.2017.2650209.

    Article  CAS  Google Scholar 

  26. E. Datta, A. Chattopadhyay, A. Mallik, and Y. Omura, Temperature dependence of analog performance, linearity, and harmonic distortion for a Ge-source tunnel FET. IEEE Trans. Electron Dev. 67(3), 810–815 (2020). https://doi.org/10.1109/TED.2020.2968633.

    Article  CAS  Google Scholar 

  27. O. K. Singh, V. Dhandapani, B. Kaur, "Investigation of temperature variation in partially extended Si1-xGex source double gate tunnel FET. In: 2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT), Bangalore, India, pp. 1-6 (2022). https://doi.org/10.1109/GCAT55367.2022.9972024

  28. P. Singh and D.S. Yadav, Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region. Appl. Phys. A 127, 671–686 (2021). https://doi.org/10.1007/s00339-021-04813-1.

    Article  CAS  Google Scholar 

  29. S. Sharma, R. Basu, and B. Kaur, Insights into temperature influence on analog/RF and linearity performance of a Si/Ge heterojunction asymmetric double gate doping less TFET. Appl. Phys. A 5, 392 (2021). https://doi.org/10.1007/s00339-021-04541-6.

    Article  CAS  Google Scholar 

  30. K.S. Singh, S. Kumar, and K. Nigam, Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Trans. Device Mater. Reliab. 20(2), 404–412 (2020). https://doi.org/10.1109/TDMR.2020.2984669.

    Article  CAS  Google Scholar 

  31. K.E. Moselund, D. Cutaia, H. Schmid, M. Borg, S. Sant, and A. Schenk, Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 1: experimental devices. IEEE Trans. Electron Dev. 63(11), 4233–4239 (2016). https://doi.org/10.1109/TED.2016.2606762.

    Article  CAS  Google Scholar 

  32. ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2016.

  33. W. Shockley and W.T. Read, Statistics of the recombinations of holes and electrons. Phys. Rev. 87(5), 835–842 (1952). https://doi.org/10.1103/PhysRev.87.835.

    Article  CAS  Google Scholar 

  34. K.N. Priyadarshani, S. Singh, and A. Naugarhiya, Dual metal double gate ge-pocket TFET (DMG-DG-Ge-pocket TFET) with hetero dielectric: DC \& analog performance projections. SILICON 14, 1593–1604 (2022). https://doi.org/10.1007/s12633-021-00955-2.

    Article  CAS  Google Scholar 

  35. A.O. Adan, T. Yoshimasu, S. Shitara, N. Tanba, and M. Fukurni, Linearity and low-noise performance of SOI MOSFETs for RF applications. IEEE Trans. Electron Dev. 49(5), 881–888 (2002). https://doi.org/10.1109/16.998598.

    Article  Google Scholar 

  36. S.H. Kim, Z.A. Jacobson, and T.-J.K. Liu, Impact of body doping and thickness on the performance of germanium-source TFETs. IEEE Trans. Electron Dev. 57(7), 1710–1713 (2010). https://doi.org/10.1109/TED.2010.2049215.

    Article  CAS  Google Scholar 

Download references

Acknowledgments

This work was supported by the SMDP-C2SD under reference letter no. 9(1)2014-MDD (NIT Delhi, Delhi, India).

Funding

No funding received.

Author information

Authors and Affiliations

  1. National Institute of Technology, New Delhi, Delhi, 110040, India

    Omendra Kr Singh, Vaithiyanathan Dhandapani & Baljit Kaur

Authors
  1. Omendra Kr Singh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vaithiyanathan Dhandapani
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Baljit Kaur
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

OKS: Writing original draft preparation, Writing—Reviewing and Editing, Conceptualization, Methodology, and Validation; VD: Supervision, Validation, Writing—Reviewing and Editing; BK: Supervision, Validation, Writing—Reviewing and Editing.

Corresponding author

Correspondence to Omendra Kr Singh.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Ethical Approval and Consent to Participate

Yes.

Consent for Publication

Yes.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Singh, O.K., Dhandapani, V. & Kaur, B. Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET). J. Electron. Mater. (2024). https://doi.org/10.1007/s11664-024-10997-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11664-024-10997-y

Keywords

Search

Navigation