Investigation of Core–Shell Junctionless Gate-Stack DG-FET in Low-Power Applications Using Charge-Based Modeling

Abstract

Modeling a stacked-gate core–shell (C-S) junctionless (JL) DG-FET and examining its suitability for low-power applications are the primary focus of the present paper. Here, charge-based analytical 2D modeling is adopted to determine the surface potential, threshold voltage, drain current and drain-induced barrier lowering (DIBL) for various core/shell thickness and shell dopant density values. The analytical model is calibrated with the experimental data available in literature, and the analytical results closely match those obtained from device simulation by Silvaco ATLAS. Next, a comparative analysis is made for C-S-JL-FET, JAM-JL-FET and traditional JL-FET, on the basis of their analog figures of merit (FOMs) [drain current ($I_d$), transconductance generation factor ($g_m/I_d$), intrinsic gain ($g_m/g_d$), total gate capacitance ($C_{\mathrm{{gg}}}$) and Early voltage ($V_{\mathrm{{EA}}}$)], and linearity FOMs [input power at the third-order intercept point ($P_{\mathrm{{IP}}3}$), second-order voltage intercept point ($V_{\mathrm{{IP}}2}$), third-order voltage intercept point ($V_{\mathrm{{IP}}3}$) and third-order intermodulation distortion ($\mathrm{{IMD3}}$)]. The performance of a cascode amplifier is also examined. The entire study reveals that all the $g_m/I_d$ ratio, $V_{\mathrm{{EA}}}$ and intrinsic gain are largest, along with significantly small OFF-current, for the C-S-JL-FET. It also offers maximum bandwidth with significantly high gain while used in a cascode amplifier. Thus, the C-S-JL-FET appears as a very promising potential candidate for low-power applications.