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Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs

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Abstract

In this paper, multi-channel nanowire (NW) performance is significantly improved by symmetric and asymmetric spacer length optimization. Device performance metrics including ON current (ION), OFF current (IOFF), and switching ratio (ION/IOFF) are improved by careful optimization of spacer length. It is observed that the NW FET exhibits the best performance with symmetric spacer lengths of source-side spacer length (LS) and drain-side spacer length (LD) of 15 nm, whereas it is observed to be LS = 15 nm and LD = 25 nm for asymmetric spacer lengths. The device exhibits the highest ION with the symmetric spacer, ensuring high-performance applications, and the lowest IOFF with the asymmetric spacer, ensuring low-power applications. In addition, an analog/RF performance comparison is made with symmetric and asymmetric spacers, and the circuit performance results are extracted using the Cadence tool through the Verilog-A interface by utilizing a lookup table approach. The common source (CS) amplifier and resistive load inverter are investigated and gain is determined. The CS amplifier exhibits higher gain (VOUT/VIN) with the asymmetric spacer. Further, a resistive load inverter is designed and demonstrated to realize optimal performance by varying the resistive load (RL) and operating voltage (VDD). The symmetric spacer exhibits better voltage transfer characteristics with RL variations.

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Acknowledgments

The authors would like to thank the department of IIT Patna for providing the TCAD Tools.

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The authors declare that they have no financial interests.

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Authors and Affiliations

  1. School of Electronics and Communication Engineering, REVA University, Bangalore, Karnataka, 560064, India

    V. Bharath Sreenivasulu

  2. School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, 632014, India

    N. Aruna Kumari & Vikas Vijayvargiya

  3. Department of Electrical Engineering and Information Technology, Technical University of Chemnitz, Chemnitz, Germany

    Vakkalakula Lokesh

  4. Department of Electronics and Communication Engineering, SR University, Warangal, India

    J. Ajayan

  5. Department of Physics, Sri Venkateswara University, Tirupati, 517 502, India

    M. Uma

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  1. V. Bharath Sreenivasulu
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  4. J. Ajayan
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Contributions

VBS: writing—original draft preparation, formal analysis, investigation, simulation, device simulation; AK: data curation, circuit simulation; VL: grammar and proof editing; A: proof review and editing; MU: review and editing; VV: resistive load inverter discussions.

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Correspondence to V. Bharath Sreenivasulu.

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Sreenivasulu, V.B., Kumari, N.A., Lokesh, V. et al. Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs. J. Electron. Mater. 52, 7268–7279 (2023). https://doi.org/10.1007/s11664-023-10618-0

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