Abstract
A double-gate heterojunction negative-capacitance tunnel field-effect transistor is proposed for OFF-current reduction with the help of a dual-material gate. In the proposed structure, the gate oxide is a layered arrangement of high-κ dielectric over low-κ dielectric to increase gate control and to eliminate lattice mismatch issues. The tangent line approximation approach is utilized in both the source-channel region and the channel-drain region to precisely model the drain current. The model is validated using two-dimensional simulations of the double-gate heterojunction dual-material gate tunnel field-effect transistor using the one-dimensional (1-D) Landau–Khalatnikov equation. The proposed topology also exhibits improvements in sub-threshold swing, ON–OFF drain current ratio, and output characteristics. The model precisely matches the device simulator results.
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SUS: Conceptualization, Writing – original draft, Methodology. BK: Investigation, Writing – original draft. HH: Investigation, Writing – original draft. JJ: Conceptualization, Writing – review and editing. AP: Supervision, Writing – review and editing. RKJ: Writing – review and editing, Supervision
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Shikha, U.S., Krishna, B., Harikumar, H. et al. OFF Current Reduction in Negative Capacitance Heterojunction TFET. J. Electron. Mater. 52, 2695–2707 (2023). https://doi.org/10.1007/s11664-023-10232-0
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DOI: https://doi.org/10.1007/s11664-023-10232-0