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Design and Qualitative Analysis of 5-nm Nanowire TFET with Spacer Engineering

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Abstract

An advanced hetero-dielectric gate oxide nanowires tunnel field-effect transistor (HD NW TET) with the spacer on both sides of the gate is proposed and analyzed. The performance characteristics of the NW TET were designed using ATLAS TCAD in 5-nm technology. In the hetero-gate dielectric NW TET, we used a nanomaterial oxide of hafnium oxide (HfO2) on the source side and silicon dioxide (SiO2) on the drain side. The advanced NW TET is proposed by adding high-k dielectric materials as nanospacers on the source and drain sides. The performance variations, hafnium oxide (HfO2) and silicon dioxide (SiO2), were used as spacers as nanomaterial oxides. The device has increased ON current while decreasing ambipolar conduction, and has a significantly smaller subthreshold swing due to its nanodimensions and nanoparticles. Therefore, the proposed dielectric material NW-TET has improved analog parameters and drain current characteristics. Therefore, the 5-nm advanced NW TET device is suitable for ultra-low-power applications.

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Acknowledgments

Authors thank to Department of Science and Technology, India, for funding the Research under the Scheme “Funds for the Improvement of S&T Infrastructure (DST-FIST)” Ref. No. SR/FST/College –110/2017

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Authors and Affiliations

  1. Center for Energy Research, Chennai Institute of Technology, Chennai, India

    J. Vishnupriyan

  2. Department of IT, Vasavi College of Engineering, Osmania University, Hyderabad, India

    S. K. ChayaDevi

  3. SRM Institute of Science and Technology, Ramapuram Campus, Chennai, Tamil Nadu, 600089, India

    V. Megala

  4. Department of Electrical and Electronics Engineering, Easwari Engineering College, Ramapuram, Chennai, India

    R. Karpagam

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  1. J. Vishnupriyan
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  2. S. K. ChayaDevi
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  3. V. Megala
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  4. R. Karpagam
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Contributions

Authors 1 and 2 (JV, SKC) compared, analyzed, and designed the NW TFET using the TCAD tool, and authors 3 and 4 (VM, RK) performed the NW TFET results and wrote the paper.

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Correspondence to V. Megala.

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Vishnupriyan, J., ChayaDevi, S.K., Megala, V. et al. Design and Qualitative Analysis of 5-nm Nanowire TFET with Spacer Engineering. J. Electron. Mater. 52, 2094–2099 (2023). https://doi.org/10.1007/s11664-022-10182-z

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