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Performance Investigation of Source Delta-Doped Vertical Nanowire TFET

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Abstract

In this paper, a source delta-doped vertical nanowire tunnel field-effect transistor is proposed, and its 2D simulations using the Silvaco ATLAS TCAD tool for ultralow-power applications are investigated. Because electron tunneling occurs in a direction parallel to the electric field at the source/channel interface, the ON-state current is higher. By incorporating a delta-doped layer in the source area, the OFF-state leakage current is further reduced. For various electrical parameters, the effects of changing the position of the delta-doped layer is investigated, as well as the effect of changing the doping concentration of the delta-doped layer and the device gate work function. It was possible to achieve a very high current ratio (ION/IOFF) of order ~ 1011 (with ION value 1.52 × 10–5 A/µm) with a very low average subthreshold slope of 18 mV/decade, and threshold voltage (VTH) of 0.57 V.

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  1. VLSI Lab, ECE Department, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, 144011, India

    Ashish Raman, Karnatakam Jaswanth Kumar, Deepti Kakkar, Ravi Ranjan & Naveen Kumar

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  1. Ashish Raman
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  2. Karnatakam Jaswanth Kumar
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  3. Deepti Kakkar
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  5. Naveen Kumar
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Correspondence to Ravi Ranjan.

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Raman, A., Kumar, K.J., Kakkar, D. et al. Performance Investigation of Source Delta-Doped Vertical Nanowire TFET. J. Electron. Mater. 51, 5655–5663 (2022). https://doi.org/10.1007/s11664-022-09840-z

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  • DOI: https://doi.org/10.1007/s11664-022-09840-z

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