Abstract
The effects of different via pad configurations on solder joint reliability during thermal cycling have been investigated. Implementation of the via-in-pad plated over (VIPPO) design configuration induced additional loading conditions for each ball grid array interconnection, resulting in a lower than expected thermal cycling performance. Thermal cycling of memory components with 0.8-mm pitch and 300-μm-diameter solder joints with and without VIPPO configuration boards have been evaluated. It was identified that specific pad design parameters degraded the thermal cycling performance. Under thermal cycling, Printed circuit boards with all-VIPPO pads and all-dog-bone pads were found to have a higher thermal cycling performance than the unevenly distributed mixed VIPPO/dog-bone pad configuration. The characteristic life for the mixed VIPPO configuration shows a performance level of 56% compared to the all-dog-bone configuration and 44% compared to the all-VIPPO configuration. Electron backscattered diffraction images revealed straining within the solder joints stemming from tension and compression due to different via pad configurations. The laser profilometer height measurement showed that dog-bone pads have larger z-axis movement than VIPPO pads, inducing localized tension within the solder joints. The heating and cooling behavior observed for VIPPO and dog-bone via pads during thermal cycling induced localized tension and compression that exacerbated joint failure and accelerated their degradation. The temperature behavior of the different pads under thermal cycling suggests that thermal cycling is a complex multi-axis phenomenon.
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References
J. Savic, M. Nagar, W. Xie, M. Ahmad, D. Senk, A. Bansal, N. Islam, P. Oh, R. Pendse, H. Choi, and S.Lee, in Proceeding of IEEE 62nd Electronic Components and Technology Conference, San Diego, CA, pp. 450–456 (2012)
H.K. Kim and K.N. Tu, Phys. Rev. B 53, 16027 (1996).
T.-K. Lee, T. Bieler, C. Kim, and H. Ma, Fundamentals of Lead-Free Solder Interconnect Technology (Berlin: Springer, 2015), pp. 169–210.
M. Kelly, M. Jeanson, T. Younger, J. Bielick, T. Lewis, and M. Ferrill, J. SMT 30, 28–36 (2017).
T.-K. Lee, B. Zhou, T. Bieler, and K.-C. Liu, J. Electron. Mater. 41, 273–282 (2012).
Q. Zhou, B. Zhou, T.-K. Lee, and T. Bieler, J. Electron. Mater. 45, 3013–3024 (2016).
Wu Mei-Ling and Jia-Shen Lan, Solder. Surf. Mount Technol, 29, 75–84 (2017).
B. Keser, R. Alvarado, A. Choi, M. Schwarz, and S. Bezuk, in Proceeding of IEEE 64th Electronic Components and Technology Conference (ECTC), Orlando, FL, pp. 925–930 (2014).
B. Titus, T. Jaiswal, and T. Dishongh, IEEE Trans. Adv. Pack. 27, 630–639 (2004).
K. Jonnalagadda, Microelectron. Reliab. 42, 253–258 (2002).
S. Perng, W. Xie, T.-K. Lee, and C. Guirguis, in Proceedings of SMTA International, Rosemont, IL, pp. 104–108 (2015)
JEDEC Standard, JESD22-A104D, Thermal Cycling, March (2009)
Bite Zhou, Quan Zhou, Thomas R. Bieler, and Tae-kyu Lee, J. Electron. Mater. 44, 895–908 (2015).
S. Wright, N. Nowell, and D. Field, Microsc. Microanal. 17, 316 (2011).
J. Angus, J. Wilkinson, and T. Britton, Mater. Today 15, 366–376 (2012).
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This work is a research collaboration project funded by Cisco systems.
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Sheikh, M., Hsiao, A., Xie, W. et al. Localized Multi-axis Loading Impact on Interconnect Thermal Cycling Performance in Via-in-Pad Plated Over (VIPPO) Board Configuration. J. Electron. Mater. 50, 699–709 (2021). https://doi.org/10.1007/s11664-020-08409-y
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DOI: https://doi.org/10.1007/s11664-020-08409-y