We report results on the interface trap density (D it) of 4H- and 6H-SiC metal–oxide–semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C–ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C–V- or G–ω-based methods, the C–ψ s method is not limited by the maximum probe frequency, therefore taking into account the “fast traps” detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density (N it) integrated from the C–ψ s method is several times that obtained from the high–low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal–oxide–semiconductor field-effect transistor (MOSFET) channels.
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Jiao, C., Ahyi, A.C., Dhar, S. et al. Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides. Journal of Elec Materi 46, 2296–2300 (2017). https://doi.org/10.1007/s11664-016-5262-2
- fast traps
- NO annealing