Skip to main content
Log in

Metal Gate (TiN, TiC, TaN) Film Stack Stress

  • Published:
Journal of Electronic Materials Aims and scope Submit manuscript

Abstract

Successful stress engineering in semiconductor device structures must consider all the contributions to the stress field including those not typically considered for stress, such as work function metal (WFM) gate layers that are used to tune to the desired work function level. These films induce stress especially since they are so close to the channel region. In this study we measure stress from blanket layer films and combinations of TiN, TiC, and TaN deposited on Hf oxide, at thicknesses that are typically used for advanced metal–oxide–semiconductor field-effect transistor (MOSFET) devices. Tungsten (W) deposited on top of the WFM layer stacks is also measured. For combination film stacks, the stress is measured after each deposition step. The induced stress from the WFM is significant, in the range of hundreds of MPa, and varies according to the thickness and processing conditions such as annealing temperature and time, etc. Results from these blanket film measurements were used as a guide for technology computer-aided design (TCAD) modeling of the stress field in FinFET structures with design rules comparable to 10-nm technology. The tensor stress components identify areas of compressive and tensile stress and with a magnitude similar to expected results. The stress field could be used to calculate the FinFET device performance, and in this case an example is provided with the relative improvement in drain current.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Y. Song, H. Zhou, X. Qiuxia, J. Luo, H. Yin, J. Yan, and H. Zhong, J. Electron. Mater. 40, 1584 (2011).

    Article  Google Scholar 

  2. M. Horstmann, A. Wei, et al., Electron Devices Meeting (2005), IEDM Technical Digest, IEEE International (2005).

  3. P.R. Chidambaram, et al., VLSI Symp. Tech. Dig. (2004), pp. 48–49.

  4. I. Ferain, C.A. Colinge, and J.-P. Colinge, Nature 479, 310 (2011).

    Article  Google Scholar 

  5. N. Singh et al., IEEE Electron. Dev. Lett. 28 (2007).

  6. N. Aneesh, et al., IEEE International Electron Devices Meeting (IEDM) (2012).

  7. S. Consiglio, and R.D. Clark, et al., ECS Trans. 41, 89 (2011).

    Article  Google Scholar 

  8. G.G. Stoney, Proc. R. Soc. Lond. Ser. A 82, 172 (1909).

    Article  Google Scholar 

  9. X. Feng, Y. Huang, and A.J. Rosakis, J. Appl. Mech. 74, 1276 (2007).

    Article  Google Scholar 

  10. C.H. Kang, et al., IEEE Electron. Dev. Lett. 29 (2008).

  11. R.C. Camarata, Prog. Surf. Sci. 46, 1 (1994).

    Article  Google Scholar 

  12. A. Kumar, K. Xiu, et al., Proceedings of SISPAD (2012), pp. 300–303.

Download references

Acknowledgements

Hugh Porter provided the high-resolution TEM image, and Vimal Kamineni coordinated the W deposition.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to A.F. Bello.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bello, A., Paul, A. & Kim, H. Metal Gate (TiN, TiC, TaN) Film Stack Stress. J. Electron. Mater. 44, 3236–3242 (2015). https://doi.org/10.1007/s11664-015-3897-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11664-015-3897-z

Keywords

Navigation