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Failure mechanisms of lead-free chip scale package interconnections under fast mechanical loading

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Abstract

The reliability of chip scale package (CSP) components against mechanical shocks has been studied by employing statistical, fractographic, and microstructural research methods. The components having high tin (Sn0.2Ag0.4Cu) solder bumps were reflow soldered with the Sn3.8Ag0.7Cu (wt.%) solder paste on Ni(P)|Au- and organic solderability preservative (OSP)-coated multilayer printed wiring boards (PWBs), and the assemblies were subjected to the standard drop test procedure. The statistically significant difference in the reliability performance was observed: the components soldered on Cu|OSP were more reliable than those soldered on Ni(P)|Au. Solder interconnections on the Cu|OSP boards failed at the component side, where cracks propagated through the (Cu,Ni)6Sn5 reaction layer, whereas interconnections on the Ni(P)|Au boards failed at the PWB side exhibiting the brittle fracture known also as “black pad.” In the first failure mode, which is not normally observed in thermally cycled assemblies, cracks propagate along the intermetallic layers due to the strong strain-rate hardening of the solder interconnections in drop tests. Owing to strain-rate hardening, the stresses in the solder interconnections increase very rapidly in the corner regions of the interconnections above the fracture strength of the ternary (Cu,Ni)6Sn5 phase leading to intermetallic fracture. In addition, because of strain-rate hardening, the recrystallization of the as-soldered microstructure is hindered, and therefore the network of grain boundaries is not available in the bulk solder for cracks to propagate, as occurs during thermal cycling. In the black pad failure mode, cracks nucleate and propagate in the porous NiSnP layer between the columnar two-phase (Ni3P+Sn) layer and the (Cu,Ni)6Sn5 intermetallic layer. The fact that the Ni(P)|Au interconnections fail at the PWB side, even though higher stresses are generated on the component side, underlines the brittle nature of the reaction layer.

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  1. Department of Electrical & Communications Engineering, Helsinki University of Technology, FIN-02015 TTK, Espoo, Finland

    T. T. Mattila & J. K. Kivilahti

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  1. T. T. Mattila
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  2. J. K. Kivilahti
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Mattila, T.T., Kivilahti, J.K. Failure mechanisms of lead-free chip scale package interconnections under fast mechanical loading. J. Electron. Mater. 34, 969–976 (2005). https://doi.org/10.1007/s11664-005-0084-7

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