Abstract
The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.
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Kizil, H., Kim, G., Steinbrüchel, C. et al. TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology. J. Electron. Mater. 30, 345–348 (2001). https://doi.org/10.1007/s11664-001-0041-z
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DOI: https://doi.org/10.1007/s11664-001-0041-z