Journal of Real-Time Image Processing

, Volume 14, Issue 3, pp 701–712 | Cite as

High-level synthesis for FPGAs: code optimization strategies for real-time image processing

  • Chao Li
  • Yanjing Bi
  • Yannick Benezeth
  • Dominique Ginhac
  • Fan Yang
Special Issue Paper


High-level synthesis (HLS) is a potential solution to increase the productivity of FPGA-based real-time image processing development. It allows designers to reap the benefits of hardware implementation directly from the algorithm behaviors specified using C-like languages with high abstraction level. In order to close the performance gap between the manual and HLS-based FPGA designs, various code optimization forms are made available in today’s HLS tools. This paper proposes a HLS source code and directive manipulation strategy for real-time image processing by taking into account the applying order of different optimization forms. Experiment results demonstrate that our approach can improve more effectively the test implementations comparing to the other optimization strategies.


Code optimization High-level synthesis FPGA Real-time image processing 



The authors would like to thank the China Scholarship Council, the CAS Pioneer Hundred Talents Program and the Conseil Régional de Bourgogne Franche-Comté for their funding of our studies.


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Copyright information

© Springer-Verlag GmbH Germany 2017

Authors and Affiliations

  1. 1.Stat Key Laboratory of Acoustics, Institute of AcousticsChinese Academy of SciencesBeijingChina
  2. 2.LE2I FRE2005 CNRS, Arts et MétiersUniv. Bourgogne Franche-ComtéDijonFrance
  3. 3.Laboratory of CPTCUniv. Bourgogne Franche-ComtéDijonFrance

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