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Hardware accelerator IP cores for real time Radar and camera-based ADAS

Abstract

The paper presents the design of HDL macrocells, working as hardware accelerators to achieve real time processing of some key functions of Advanced Driver Assistance Systems (ADAS). Particularly, the macrocells process in real time images from Radar and video-camera sensors implementing computing-intensive operations such as: pixel-level filtering, correction of distortions in large field-of-view cameras, multi-camera image fusion for panoramic view of car’s surround, traffic and road signs recognition, detection of obstacles for collision avoidance, and estimation of their distance and speed. The HDL macrocells are fully configurable and are synthesized in low-cost Artix-7 FPGA family, satisfying automotive-grade requirements. They can be integrated as accelerators in embedded hardware–software platforms to build a complete ADAS solution. To this aim, the macrocells have been synthesized also in a Zynq FPSoC. With respect to the state of the art, the proposed macrocells stand for their low-power and real time performance .

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Acknowledgements

Discussions with R. Massini, B. Neri, B. Carnevale, and E. Franchi, from University of Pisa, are acknowledged.

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Correspondence to Sergio Saponara.

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Saponara, S. Hardware accelerator IP cores for real time Radar and camera-based ADAS. J Real-Time Image Proc 16, 1493–1510 (2019). https://doi.org/10.1007/s11554-016-0657-0

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Keywords

  • Real time processing
  • Hardware accelerator
  • ADAS (Advanced Driver Assistance System)
  • IP (Intellectual Property) digital macrocells
  • FPGA/FPSoC (Field-Programmable Gate-Array/System-on-Chip)
  • HDL (Hardware Description Language)