On the design of optimal 2D filters for efficient hardware implementations of image processing algorithms by using power-of-two terms
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In this paper, we present a general approximation for 2D filters by using only power-of-two terms. This enables to easily implement these filters in electronic devices such as FPGA and ASIC just by using simple hardware shifters and adders/subtractors. Consequently, no division and no multiplication operators are required, which can reduce the memory and the power needed for computing operations such as convolution. Instead of using only additions and power-of-two terms for representing a number like in the standard binary decomposition, our model also uses subtractions for representing and approximating numbers. In addition, we propose a binary tree structure for computing a minimal representation in power-of-two terms in such a way that hardware shifters used for performing a convolution with a low-pass filter for example are well reduced to their minimum. Based on some experiments performed for contrast enhancement, which is a common image processing operation, we have noticed that good results can be obtained using our approximation in terms of image quality, hardware resources, and power consumption when compared to some other binary representations.
KeywordsNumber representation Multipliers Logical shift operators FPGA 2D filters Image processing Contrast enhancement Minimal representation Binary tree
The completion of this research was made possible thanks to the Natural Sciences and Engineering Research Council of Canada (NSERC) and the Alberta Informatics Circle of Research Excellence (iCORE)/Alberta Innovates—Technology Futures (AITF).
- 6.Yu, W.W.H., Xing, S.: Fixed-point multiplier evaluation and design with FPGA. In: Proceedings of SPIE—The International Society for Optical Engineering, vol. 3844, pp. 153–161 (1999)Google Scholar
- 9.Baudin, R., Lesthievent, G.: Design of FIR filters with sum of power-of-two representation using simulated annealing. In: 7th Advanced Satellite Multimedia Systems Conference and the 13th Signal Processing for Space Communications Workshop (ASMS/SPSC), pp. 339–345 (2014)Google Scholar
- 11.Petrlik, J., Sekanina, L.: Multiobjective evolution of approximate multiple constant multipliers. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 116–119 (2013)Google Scholar
- 12.Hsiao, P.Y., Chen, C.H., Chou, S.S., Li, L.T., Chen, S.J.: A parameterizable digital-approximated 2D Gaussian smoothing filter for edge detection in noisy image. In: IEEE International Symposium on Circuits and Systems, pp. 3189–3192 (2006)Google Scholar
- 19.Guo, Z., Xu, W., Chai, Z.: Image edge detection based on FPGA. In: International Symposium on Distributed Computing and Applications to Business Engineering and Science, pp. 169–171 (2010)Google Scholar
- 21.Horé, A., Ziou, D.: Image quality metrics: PSNR vs. SSIM. In: International Conference on Pattern Recognition (ICPR), pp. 2366–2369 (2010)Google Scholar