A dynamically reconfigurable architecture system for time-varying image constraints (DRASTIC) for motion JPEG

Abstract

We propose a dynamically reconfigurable system for time-varying image constraints (DRASTIC) for applications in video communications. DRASTIC defines a framework for both joint and independent optimization of dynamic power, image quality, and bitrate subject to different constraint scenarios. We demonstrate DRASTIC for intra-mode video encoding for MJPEG. However, since the DCT is critical component of most video coding standards, our approach can be extended to modern standards such as AVC (H.264), and emerging standards such as HEVC (H.265), and VP9. Based on a hardware–software co-design approach, we define a family of scalable 2D DCT hardware modules that are jointly optimized with the quality factor (in software). We generate a total of 1,280 configurations of which 841 were found to be Pareto optimal. For full 2D DCT calculation, the results indicate that the proposed method is DRASTIC mode implementation at least as good or significantly better than any previously published implementation. A scalable, real-time controller is used for selecting an appropriate configuration so as to meet time-varying constraints. The real-time controller is shown to satisfy the constraints of different communications modes (e.g., minimum dynamic power, maximum image quality, etc.) as well as to adapt to mode changes. Empirically, we have found that the DRASTIC controller adapts to meet the new constraints within five video frames of a mode change. Overall, the proposed approach yields significant savings over the use of comparable static architectures.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

References

  1. 1.

    Huang, Y.-W., Hsieh, B.-Y., Chen, T.-C., Chen, L.-G.: Analysis, fast algorithm, and vlsi architecture design for h.264/avc intra frame coder. IEEE Trans. Circuits Syst. Video Technol. 15(3), 378–401 (2005)

    Article  Google Scholar 

  2. 2.

    Chen, L., Shashidhar, N., Liu, Q.: Scalable secure MJPEG video streaming. In: 2012 26th International Conference on Advanced Information Networking and Applications Workshops (WAINA), pp. 111–115 (2012)

  3. 3.

    Du, Q., Qin, H., Tang, J., Li, X.: Design of the arm based remote surveillance system. In: 2012 3rd International Conference on System Science, Engineering Design and Manufacturing Informatization (ICSEM), vol. 1, pp. 336–338 (2012)

  4. 4.

    Ko, H.-Y., Lee, J.-H., Kim, J.-O.: Implementation and evaluation of fast mobile VNC systems. IEEE Trans. Consum. Electron. 58(4), 1211–1218 (2012)

    Article  Google Scholar 

  5. 5.

    Wang, Z., Bovik, A., Sheikh, H., Simoncelli, E.: Image quality assessment: from error visibility to structural similarity. IEEE Trans. Image Process. 13(4), 600–612 (2004)

    Article  Google Scholar 

  6. 6.

    Jiang, Y., Pattichis, M.: Dynamically reconfigurable DCT architecture based on bitrate, power, and image quality considerations. In: 2012 International Conference on Image Processing, pp. 2465–2468 (2012)

  7. 7.

    Jiang, Y., Pattichis, M.: A dynamically reconfigurable DCT architecture for maximum image quality subject to dynamic power and bitrate constraints. In: 2012 IEEE Southwest Symposium on Image Analysis and Interpretation (SSIAI), pp. 189–192 (2012)

  8. 8.

    Xilinx, Inc.; Application Note: Virtex Series; XAPP151 (v1.7); "Virtex Series Configuration Architecture User Guide", Oct. 20, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; pp. 1–45

  9. 9.

    Huang, J., Parris, M., Lee, J., Demara, R.F.: Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embed. Comput. Syst. 9(1), 1–18 (2009)

    Article  Google Scholar 

  10. 10.

    Huang, J., Lee, J.: A self-reconfigurable platform for scalable DCT computation using compressed partial bitstreams and blockram prefetching. IEEE Trans. Circuits Syst. Video Technol. 19(11), 1623–1632 (2009)

    Article  Google Scholar 

  11. 11.

    Huang, J., Lee, J.: Reconfigurable architecture for ZQDCT using computational complexity prediction and bitstream relocation. IEEE Embed. Syst. Lett. 3(1), 1–4 (2011)

    Article  Google Scholar 

  12. 12.

    Llamocca, D., Pattichis, M.: A dynamically reconfigurable pixel processor system based on power/energy-performance-accuracy optimization. IEEE Trans. Circuits Syst. Video Technol. 23(3), 488–502 (2013)

    Article  Google Scholar 

  13. 13.

    Kannangara, C., Richardson, I., Miller, A.J.: Computational complexity management of a real-time h.264/avc encoder. IEEE Trans. Circuits Syst. Video Technol. 18(9), 1191–1200 (2008)

    Article  Google Scholar 

  14. 14.

    He, Z., Liang, Y., Chen, L., Ahmad, I., Wu, D.: Power–rate–distortion analysis for wireless video communication under energy constraints. IEEE Trans. Circuits Syst. Video Technol. 15(5), 645–658 (2005)

    Article  Google Scholar 

  15. 15.

    He, Z., Cheng, W., Chen, X.: Energy minimization of portable video communication devices based on power–rate–distortion optimization. IEEE Trans. Circuits Syst. Video Technol. 18(5), 596–608 (2008)

    Article  Google Scholar 

  16. 16.

    Li, X., Wien, M., Ohm, J.-R.: Rate–complexity–distortion optimization for hybrid video coding. IEEE Trans. Circuits Syst. Video Technol. 21(7), 957–970 (2011)

    Article  Google Scholar 

  17. 17.

    Madisetti, A., Jr Willson, A.N.: A 100 MHz 2-d 8 × 8 DCT/IDCT processor for HDTV applications. IEEE Trans. Circuits Syst. Video Technol. 5(2), 158–165 (1995)

    Article  Google Scholar 

  18. 18.

    Lee, Y.-P., Chen, T.-H., Chen, L.-G., Chen, M.-J., Ku, C.-W.: A cost-effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method. IEEE Trans. Circuits Syst. Video Technol. 7(3), 459–467 (1997)

    Article  Google Scholar 

  19. 19.

    Hsiao, S.-F., Shiue, W.-R., Tseng, J.-M.: A cost-efficient and fully-pipelinable architecture for DCT/IDCT. IEEE Trans. Consum. Electron. 45(3), 515–525 (1999)

    Article  Google Scholar 

  20. 20.

    Cheng, K.-H., Huang, C.-S., Lin, C.-P.: The design and implementation of DCT/IDCT chip with novel architecture. In: The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings ISCAS 2000 Geneva, vol. 4, pp. 741–744 (2000)

  21. 21.

    Hsiao, S.-F., Shiue, W.-R., Tseng, J.-M.: Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log2n. IEE Proc. Vis. Image Signal Process. 147(5), 400–408 (2000)

    Article  Google Scholar 

  22. 22.

    Agostini, L., Silva, I., Bampi, S.: Pipelined fast 2d DCT architecture for JPEG image compression. In: 14th Symposium on Integrated Circuits and Systems Design, pp. 226–231 (2001)

  23. 23.

    Kusuma, E., Widodo, T.L Fpga implementation of pipelined 2d-DCT and quantization architecture for JPEG image compression. In: 2010 International Symposium in Information Technology (ITSim), June 2010, vol. 1, pp. 1–6 (2010)

  24. 24.

    Chen, W.-H., Smith, C., Fralick, S.: A fast computational algorithm for the discrete cosine transform. IEEE Trans. Commun. 25(9), 1004–1009 (1997)

    Article  MATH  Google Scholar 

  25. 25.

    Xanthopoulos, T., Chandrakasan, A.: A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. IEEE J. Solid-State Circuits 35(5), 740–750 (2000)

    Article  Google Scholar 

  26. 26.

    Kim, D.W., Kwon, T.W., Seo, J.M., Yu, J.K., Lee, S.K., Suk, J.H., Choi, J.R.: A compatible DCT/IDCT architecture using hardwired distributed arithmetic. In: The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, May 2001, vol. 2, pp. 457–460 (2001)

  27. 27.

    Yu, S., Swartziander, J.: DCT implementation with distributed arithmetic. IEEE Trans. Comput. 50(9), 985–991 (2001)

    Article  Google Scholar 

  28. 28.

    Chungan, P., Xixin, C., Dunshan, Y., Xing, Z.: A 250 MHz optimized distributed architecture of 2d 8 × 8 DCT. In: 7th International Conference on ASIC. ASICON ’07, Oct 2007, pp. 189–192 (2007)

  29. 29.

    Lim, H., Yim, C., Swartzlander, Jr., E.E.: Finite word-length effects of an unified systolic array for 2-d DCT/IDCT. In: Proceedings of International Conference on Application Specific Systems, Architectures and Processors. ASAP 96, Aug 1996, pp. 35–44 (1996)

  30. 30.

    Chiper, D., Swamy, M., Ahmad, M., Stouraitis, T.: Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST. IEEE Trans. Circuits Syst. I: Reg. Papers 52(6), 1125–1137 (2005)

    Article  Google Scholar 

  31. 31.

    Meher, P.: Systolic designs for DCT using a low-complexity concurrent convolutional formulation. IEEE Trans. Circuits Syst. Video Technol. 16(9), 1041–1050 (2006)

    Article  Google Scholar 

  32. 32.

    Hu, Y.H., Wu, Z.: An efficient cordic array structure for the implementation of discrete cosine transform. IEEE Trans. Signal Process. 43(1), 331–336 (1995)

    Article  Google Scholar 

  33. 33.

    Yu, S., Jr Swartzlander, E.E.: A scaled DCT architecture with the cordic algorithm. IEEE Trans. Signal Process. 50(1), 160–167 (2002)

    Article  Google Scholar 

  34. 34.

    Guo, J.-I., Ju, R.-C., Chen, J.-W.: An efficient 2-d DCT/IDCT core design using cyclic convolution and adder-based realization. IEEE Trans. Circuits Syst. Video Technol. 14(4), 416–428 (2004)

    Article  Google Scholar 

  35. 35.

    Madanayake, A., Cintra, R., Onen, D., Dimitrov, V., Rajapaksha, N., Bruton, L., Edirisuriya, A.: A row-parallel 8 × 8 2-d DCT architecture using algebraic integer-based exact computation. IEEE Trans. Circuits Syst. Video Technol. 22(6), 915–929 (2012)

    Article  Google Scholar 

  36. 36.

    Seshadrinathan, K., Bovik, A.: Motion tuned spatio-temporal quality assessment of natural videos. IEEE Trans. Image Process. 19(2), 335–350 (2010)

    MathSciNet  Article  MATH  Google Scholar 

  37. 37.

    Seshadrinathan, K., Soundararajan, R., Bovik, A., Cormack, L.: Study of subjective and objective quality assessment of video. IEEE Trans. Image Process. 19(6), 1427–1441 (2010)

    MathSciNet  Article  MATH  Google Scholar 

  38. 38.

    Seshadrinathan, K., Soundararajan, R., Bovik, A.C., Cormack, L.K.: A subjective study to evaluate video quality assessment algorithms. In: SPIE Proceedings Human Vision and Electronic Imaging, Jan 2010 (2010)

  39. 39.

    Ou, Y.-F., Ma, Z., Wang, Y.: Modeling the impact of frame rate and quantization stepsizes and their temporal variations on perceptual video quality: a review of recent works. In: 2010 44th Annual Conference on Information Sciences and Systems (CISS), pp. 1–6 (2010)

  40. 40.

    Hsieh, C.-H.: A zonal JPEG. In: International Conference on Information Technology: Coding and Computing. ITCC 2005, April 2005, vol. 2, pp. 756–757 (2005)

  41. 41.

    Park, J., Choi, J.H., Roy, K.: Dynamic bit-width adaptation in DCT: an approach to trade off image quality and computation energy. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(5), 787–793 (2010)

    Article  Google Scholar 

  42. 42.

    Sheikh, H., Sabir, M., Bovik, A.: A statistical evaluation of recent full reference image quality assessment algorithms. IEEE Trans. Image Process. 15(11), 3440–3451 (2006)

    Article  Google Scholar 

  43. 43.

    Seeling, P., Reisslein, M.: Video transport evaluation with h.264 video traces”, IEEE Commun. Surv. Tutor. 14(4):1142–1165 [Online] (2011). http://trace.eas.asu.edu/yuv/

  44. 44.

    Tumeo, A., Monchiero, M., Palermo, G., Ferrandi, F., Sciuto, D.: A pipelined fast 2d-DCT accelerator for fpga-based socs. In: IEEE Computer Society Annual Symposium on VLSI. ISVLSI ’07, March 2007, pp. 331–336 (2007)

  45. 45.

    Sharma, V., Mahapatra, K., Pati, U.: An efficient distributed arithmetic based vlsi architecture for DCT. In: 2011 International Conference on Devices and Communications (ICDeCom), Feb 2011, pp. 1–5 (2011)

Download references

Acknowledgments

This material is based upon work supported by the National Science Foundation under NSF AWD CNS-1422031.

Author information

Affiliations

Authors

Corresponding author

Correspondence to Marios S. Pattichis.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Jiang, Y., Pattichis, M.S. A dynamically reconfigurable architecture system for time-varying image constraints (DRASTIC) for motion JPEG. J Real-Time Image Proc 14, 395–411 (2018). https://doi.org/10.1007/s11554-014-0460-8

Download citation

Keywords

  • MJPEG
  • FPGA
  • DCT
  • Zonal
  • Finite word length
  • Dynamic partial reconfiguration
  • Dynamically reconfigurable computing