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The FPGA implementation of a one-bit-per-pixel image registration algorithm

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Abstract

The calculation of the motion observed between two images of the same scene is required for many applications such as video compression, panoramic stitching and optic flow algorithms for vehicle navigation. The particular application that we focus on in this paper is the need for small light-weight vehicles, such as unmanned ground or air vehicles, to sense their own motion for use in autonomous navigation algorithms. As the processing is ideally performed on-board these vehicles, there are severe restrictions on the processing environment available to perform the optic flow calculations. This has led to the development of FPGA solutions to calculate optic flow. However the most recent approaches still have extensive on-board memory requirements and make use of complex processing operations such as multiplication and matrix inversion. We present an FPGA implementation of a low complexity version of the Lucas–Kanade registration algorithm. This algorithm operates on one-bit images instead of the standard eight-bit approach and consequently can utilize simple logic operations such as exclusive-or rather than multiplications and also makes very efficient use of the available internal memory and resources.

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  1. UNSW Australia, UNSW Canberra at ADFA, Canberra, Australia

    An Hung Nguyen, Mark R. Pickering & Andrew Lambert

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  1. An Hung Nguyen
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  2. Mark R. Pickering
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  3. Andrew Lambert
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Correspondence to An Hung Nguyen.

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Nguyen, A.H., Pickering, M.R. & Lambert, A. The FPGA implementation of a one-bit-per-pixel image registration algorithm. J Real-Time Image Proc 11, 799–815 (2016). https://doi.org/10.1007/s11554-014-0420-3

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  • DOI: https://doi.org/10.1007/s11554-014-0420-3

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