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Journal of Real-Time Image Processing

, Volume 12, Issue 1, pp 107–122 | Cite as

Complexity scalability for real-time HEVC encoders

  • Guilherme Correa
  • Pedro Assuncao
  • Luciano Agostini
  • Luis A. da Silva Cruz
Original Research Paper

Abstract

The high efficiency video coding (HEVC) standard achieves improved compression efficiency in comparison to previous standards at the cost of much higher computational complexity and consequently longer processing times, which may compromise real-time software-based video encoding, especially at high resolutions. This article addresses the problem of enabling complexity scalability in HEVC encoders by trading-off processing time for rate–distortion (R–D) performance in a controlled manner. The proposed method is based on dynamic constraining of HEVC coding treeblocks (CTBs) by limiting the prediction block (PB) shapes and the maximum tree depth used in each CTB, to decrease the number of R–D evaluations performed in the optimization process. The complexity-scalable encoder is capable of adjusting the processing time used in each group of pictures, according to a predefined target. The results show that processing times can be scaled down to 50 % with negligible R–D performance losses and down to 20 % at a maximum BD-PSNR decrease of 1.41 dB, which is acceptable in many applications and in power constrained devices. The simplicity of the scaling algorithm and the possibility of continuous adjustment of the scaling factor make it amenable to control real-time software-based HEVC video encoders.

Keywords

High efficiency video coding (HEVC) Video coding Real time Computational complexity 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Guilherme Correa
    • 1
  • Pedro Assuncao
    • 2
  • Luciano Agostini
    • 3
  • Luis A. da Silva Cruz
    • 1
  1. 1.Instituto de Telecomunicações (IT), Polo IIUniversidade de CoimbraCoimbraPortugal
  2. 2.Instituto de Telecomunicações (IT)LeiriaPortugal
  3. 3.Group of Architectures and Integrated CircuitsFederal University of PelotasPelotasBrazil

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