Advertisement

Journal of Real-Time Image Processing

, Volume 9, Issue 1, pp 31–45 | Cite as

Modified stable Euler-number algorithm implementation for real-time image binarization

  • Naeem AbbasiEmail author
  • Jacques Athow
  • Aishy Amer
Special Issue
  • 265 Downloads

Abstract

The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.

Keywords

Stable Euler Number FPGA Image binarization Pipelined architecture Real-time 

References

  1. 1.
    Li, W., Huading, J., Binjie, L.: A new binarization algorithm based on maximum gradient of histogram. In: Fourth International Conference on Image and Graphics (ICIG), pp. 368–371 (2007)Google Scholar
  2. 2.
    Berry, F., Chalimbaud, P.: Embedded active vision system based on FPGA architecture. EURASIP J.Embed. Syst. 12 (2007)Google Scholar
  3. 3.
    Ratnayake, K.; Amer, A.: An FPGA-based implementation of spatio-temporal object segmentation. In: Proceedings of the IEEE International Conference on Image Processing (ICIP), pp. 3265–3268 (2006)Google Scholar
  4. 4.
    Ashari, R.I., Hornsey, E.: FPGA implementation of real-time adaptive image thresholding. In: Proceedings of the SPIE, vol. 5578, pp. 410–419 (2004)Google Scholar
  5. 5.
    Paul, L.R.: Thresholding for change detection. In: Sixth IEEE International Conference on Computer Vision, pp. 274–279 (1998)Google Scholar
  6. 6.
    Al-Kofahi, O., Roysam, B., Radke, R.J., Andra, S.: Image change detection algorithms: a systematic survey. IEEE Transact Image Process 14, 294–307 (2005)CrossRefMathSciNetGoogle Scholar
  7. 7.
    Gray, S.B.: Local properties of binary images in two dimensions. IEEE Transact Compu 20, 551–561 (1971)CrossRefzbMATHGoogle Scholar
  8. 8.
    O’Gorman, L.: Binarization and multi-thresholding of document imnages using connectivity. In: Symposium on Document Analysis and Information Retrieval, pp. 237–252 (1994)Google Scholar
  9. 9.
    Pikaz, A., Averbuch, A.: Digital image thresholding based on topological stable state. Pattern Recognit 29, 829–843 (1996)CrossRefGoogle Scholar
  10. 10.
    Rosin, P., Ellis, T.: Image difference threshold strategies and shadow detection. In: British Machine Vision Conference, pp. 347–356 (1995)Google Scholar
  11. 11.
    Cope, B., Cheung, P., Luk, W., Howes, L. Performance comparison of graphics processors to reconfigurable logic: a case study. Comput. IEEE Transact. 59(4), 433–448 (2010)CrossRefMathSciNetGoogle Scholar
  12. 12.
    Kundu, M.K., Bishnu, A., Acharya, T., Dey, S., Bhattacharya, B.B.: A co-processor for computing the euler number of a binary image using divide-and-conquer strategy. Fundamenta Informaticae 76, 75–89 (2007)zbMATHMathSciNetGoogle Scholar
  13. 13.
    Hesselbarth, S., Schunemann, T., Pirsch, P., Flatt, H., Blume, S.: A parallel hardware architecture for connected component labeling based on fast label merging. In: International Conference on Application-Specific systems, Architectures and Processors (ASAP 2008), pp. 144–149 (2008)Google Scholar
  14. 14.
    Owall, V., Hedberg, H., Kristensen, F.: Implementation of a labeling algorithm based on contour tracing with feature extraction. In: IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 1101–1104 (2007)Google Scholar
  15. 15.
    Kundu, M.K., Murthy, C.A., Acharya, T., Bishnu, A., Bhattacharya, B.B.: On-chip computation of euler number of a binary image for efficient database search. In: Proceedings of the International Conference on Image Processing (ICIP), pp. 310–313 (2001)Google Scholar
  16. 16.
    Okuma, S., Yano, Y., Hashimiyama, T.: On-line filter generation for binary image processing using FPGA. In: Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC 99), vol. 5, pp. 565–570 (1999)Google Scholar
  17. 17.
    Iacoviello, D., Iacoviello, F., Santis, A.D., Bartolomeo, O.D.: Optimal binarization of images by neural networks for morphological analysis of ductile cast iron. Pattern. Anal. Appl. 10, 125–133 CrossRefGoogle Scholar
  18. 18.
    Abbasi, N., Athow, J., Amer, A.: Effect of mask size on the cost/performance of spatial property calculator. Appendix A in: A real-time FPGA architecture of a modified stable Euler-number algorithm for Image binarization, Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada, Technical Report vidpro-TR-01-12,http://users.encs.concordia.ca/amer/paper/report/SENA.pdf (2012)
  19. 19.
    Parhi, K.K.: VLSI digital signal processing systems, design and implementation. Blackwell, London (1999)Google Scholar
  20. 20.
    Sutter, G., Dechamps, J.P., Bioul, G.: Synthesis of arithmetic circuits. Wiley Interscience Edition, Blackwell, London (2006)Google Scholar
  21. 21.
    HOL.: Higher order logic theorem prover. http://hol.sourceforge.net/ Jun 2012
  22. 22.
    Snidaro, L., Foresti, G.L. Real-time thresholding with euler numbers. Pattern Recognit Lett 24, 1533–1544 (2003)CrossRefzbMATHGoogle Scholar
  23. 23.
    Amer, A.: Memory-based spatio-temporal real-time object segmentation. In: Proceedings of the SPIE, International Symposium on Electronic Imaging, Conference on Real-Time Imaging (RTI), vol. 5012, pp. 10–21 (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringConcordia UniversityQCCanada

Personalised recommendations