Journal of Real-Time Image Processing

, Volume 8, Issue 1, pp 111–125 | Cite as

A multi-processor NoC-based architecture for real-time image/video enhancement

Special Issue

Abstract

The paper presents a multi-processor architecture for real-time and low-power image and video enhancement applications. Differently from other state-of-the-art parallel architectures the proposed solution is composed of heterogeneous tiles. The tiles have computational and memory capabilities, support different algorithmic classes and are connected by a novel Network-on-Chip (NoC) infrastructure. The proposed packet-switched data transfer scheme avoids communication bottlenecks when more tiles are working concurrently. The functional performances of the NoC-based multi-processor architecture are assessed by presenting the achieved results when the platform is programmed to support different enhancement algorithms for still images or videos. The implementation complexity of the NoC-based multi-tile platform, integrated in 65 nm CMOS technology, is reported and discussed.

Keywords

Image enhancement Real-time image/video processing Network-on-Chip (NoC) Digital IP cells Multi-Processor System on Chip (MPSoC) 

Notes

Acknowledgment

This work has been partially supported by the EU integrated project SHAPES of the 6th framework programme in collaboration with STMicroelectronics, particularly the group of Dr. M. Coppola (AST, Grenoble).

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Copyright information

© Springer-Verlag 2011

Authors and Affiliations

  1. 1.Department of Information EngineeringUniversity of PisaPisaItaly
  2. 2.Consorzio Pisa Ricerche scarlPisaItaly

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