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Model-based mapping of reconfigurable image registration on FPGA platforms

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Abstract

Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA

    Mainak Sen, Yashwanth Hemaraj, William Plishker, Raj Shekhar & Shuvra S. Bhattacharyya

  2. Institute for Advanced Computer Studies, University of Maryland, College Park, MD, 20742, USA

    Mainak Sen, William Plishker & Shuvra S. Bhattacharyya

  3. Department of Diagnostic Radiology, University of Maryland, Baltimore, MD, 21201, USA

    Yashwanth Hemaraj, William Plishker & Raj Shekhar

  4. Cisco Systems, San Jose, CA, USA

    Mainak Sen

  5. Texas Instruments, Germantown, MD, USA

    Yashwanth Hemaraj

Authors
  1. Mainak Sen
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  2. Yashwanth Hemaraj
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  3. William Plishker
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  4. Raj Shekhar
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  5. Shuvra S. Bhattacharyya
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Correspondence to Mainak Sen.

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Sen, M., Hemaraj, Y., Plishker, W. et al. Model-based mapping of reconfigurable image registration on FPGA platforms. J Real-Time Image Proc 3, 149–162 (2008). https://doi.org/10.1007/s11554-008-0075-z

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  • DOI: https://doi.org/10.1007/s11554-008-0075-z

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